Not coherent cache DMA for G3/G4 CPUs: clarification needed

[Benjamin Herrenschmidt]

> In this case the problem is double mapping with inconsistent attributes
> (through BAT and page tables I assume). 

Yes.
 
> > On POWER4, 970 and later, the chip guys confirmed that the problem is
> > real though. Not only bcs of prefetch but also speculative execution
> > which can cause the chip to do a load that will never actually be
> > executed. Imagine for example a loop walking an array, the chip might
> > speculatively load elements beyond the array by speculatively executing
> > beyond the branch that ends the loop.
> 
> Even if the page has the guarded bit set?

The BAT mapping doesn't have G set.

Ben.