[PATCH] ppc32: make sure we have an L3 before touch its control register

Kumar Gala galak at freescale.com
Fri Sep 23 05:51:34 EST 2005


Can you take a look at this.  I think its pretty straight forward and if 
your ok with it please forward on to linus.

- kumar


Some variants of 745x may not actually have the L3CR register.  Since
we mark which variants of 745x have L3CRs in the cputable we can
use that information to ensure that the mfspr L3CR will not cause
an exception in the processors that don't have the register.

Signed-off-by: Kumar K. Gala <kumar.gala at freescale.com>

commit f706b6046f1fee29bdf3081dd783f7e482012165
tree 6d42ee61458ec94ac7d4567e3f0383dd1e47a537
parent d8ac10639b6a1ed900efbee38c18baaca31e64dc
author Kumar K. Gala <kumar.gala at freescale.com> Thu, 22 Sep 2005 14:47:52 -0500
committer Kumar K. Gala <kumar.gala at freescale.com> Thu, 22 Sep 2005 14:47:52 -0500

 arch/ppc/kernel/cpu_setup_6xx.S |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/ppc/kernel/cpu_setup_6xx.S b/arch/ppc/kernel/cpu_setup_6xx.S
--- a/arch/ppc/kernel/cpu_setup_6xx.S
+++ b/arch/ppc/kernel/cpu_setup_6xx.S
@@ -212,9 +212,11 @@ setup_745x_specifics:
 	 * the firmware. If any, we disable NAP capability as
 	 * it's known to be bogus on rev 2.1 and earlier
 	mfspr	r11,SPRN_L3CR
 	andis.	r11,r11,L3CR_L3E at h
 	beq	1f
 	lwz	r6,CPU_SPEC_FEATURES(r5)
 	andi.	r0,r6,CPU_FTR_L3_DISABLE_NAP
 	beq	1f

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