[PATCH] powerpc: Merge align.c

Becky Bruce becky.bruce at freescale.com
Wed Nov 16 13:19:58 EST 2005


Yeah,  I clearly shouldn't run testcases at 11pm, because I got in a 
rush and only confirmed that lmw/stmw were actually taking the 
exception.  Those 2 are working beautifully.  To test the others, I 
need to run on a different board which, of course,  isn't bootable at 
the moment.  As soon as I can get that up and running, I'll try some of 
the other cases and let you know how it goes......

BTW, Based on the pile of docs I have here, I think the list of 
alignment-exception-causing events on FSL's current parts (603, 603e, 
750, 74x, 74xx, e500) is:

- lmw/stmw (all procs, non-word aligned)
- single and double precision floating point ld/st ops (non-E500, non 
data size aligned)
- dcbz to WT or CI memory (all procs)
- dcbz with cache disabled (all procs but 603e?)
- misaligned little endian accesses (603e)
- lwarx/stwcx (all procs)
- multiple/string with LE set (750, 603e, 7450, 7400)
- eciwx/ecowx (750, 7450, 7400)
- a couple of others related to vector processing

If anybody knows offhand of something missing there, let me know.


On Nov 14, 2005, at 11:35 PM, Benjamin Herrenschmidt wrote:

> On Mon, 2005-11-14 at 23:10 -0600, Becky Bruce wrote:
> > Ben,
> >
> > I've just done some basic testing of lmw/stmw, lwz/stw, lhx/sth,
> > lfs/stfs, and lfd/stfd misaligned across a doubleword boundary, and
> > everything looks good so far.   I'll check out the byte reversals 
> and a
> > few other forms tomorrow.
> Excellent, thanks ! BTW. Make sure you test these one CPUs that 
> actually
> trap on misaligned accesses :) Best is probably to do the misaligned
> access accross a page boundary, that's what most CPUs can do.
> Ben.

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