kernel hang on 'now booting the kernel'
Ali Paikan
ali at pctlinux.com
Sun Dec 25 21:18:30 EST 2005
Dear Sir,
I am a student and I tried to install Linux on ML300 board. I need that for
doing my final project but I have many problems.
I compiled the open source PowerPC kernel (linuxppc_2_4_devel) with a cross
compiler which I built it by Dan Kegel cross tools. Before compiling, I
updated xparameters_ml300.h according to my base system design from Xilinx EDK.
Next, I tried to download kernel ELF file to board and every thing seen well.
But My kernel hanged up when it was going to load main kernel image with show
this message on serial console:
loaded at: 00400000 004B01E4
board data at: 004AD13C 004AD154
relocated to: 00405648 00405660
zimage at: 00405C13 004AC65E
avail ram: 004B1000 08000000
Linux/PPC load: console=ttyS0,9600 ip=off root=/dev/xsysace/disc0/part3 rw
Uncompressing Linux...done.
Now booting the kernel
I debugged the kernel and results showed memory initialized and load_kernel
function decompressed image into address 0x0 as well. (I can see tree NOP
instructions from address 0x0).
But, I am not sure about next step in jumping to address 0x000C and running
the main part of kernel.
I wondered more when I tried to make a Xilinx System ACE file with Impact.
It failed too with showing this fatal error:
FATAL_ERROR:GuiUtilities:WinApp.c:710:$Revision - This application has
discovered an exceptional condition from which it cannot recover. Process
will terminate. To resolve this error, please consult the Answers Database
and other online resources at http://support.xilinx.com. If you need further
assistance, please open a Webcase by clicking on the "WebCase" link at http://support.xilinx.com.
I don't have any problem for making system ace from other ELF files.
Might it be for my bad compilation?
Is my base system building for FPGA not correct?
Where is my wrong?
For more information I attached my all configuration and log files at end of
this mail.
I am too great if you help me in this case and I look forward to hearing from you.
Sorry my pure English!
Sincerely,
Ali Paikan
Cross compiler option:
CONFIG_TARGET="powerpc-405-linux-gnu"
CONFIG_TARGET_CFLAGS="-O -mcpu=405"
CONFIG_GCC_EXTRA_CONFIG="--with-cpu=405 --enable-cxx-flags=-mcpu=405"
CONFIG_GLIBC_EXTRA_CONFIG="—without-fp"
powerpc-405-linux-gnu-objdump -h:
zImage.: file format elf32-powerpc
Sections:
Idx Name Size VMA LMA File off Algn
0 .text 00004798 00400000 00400000 00010000 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
1 .data 00095000 00405000 00405000 00015000 2**2
CONTENTS, ALLOC, LOAD, DATA
2 .bss 000031e0 0049a000 _u48 ?49a000 000aa000 2**2
ALLOC
3 .note.GNU-stack 00000000 00000000 00000000 000aa000 2**0
CONTENTS, READONLY
Xparameters_ml300.h :
/*********************************************************_u42 ?********
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 7.1 EDK_H.10.4
* DO NOT EDIT.
*
* Copyright (c) 2005 Xilinx, Inc. All rights reserved.
*
* Description: Driver parameters
*
*******************************************************************/
#define XPAR_XUARTLITE_NUM_INSTANCES 1
#define XPAR_RS232_UART_1_BASEADDR 0x40600000
#define XPAR_RS232_UART_1_HIGHADDR 0x4060FFFF
#define XPAR_RS232_UART_1_DEVICE_ID 0
#define XPAR_RS232_UART_1_BAUDRATE 9600
#define XPAR_RS232_UART_1_USE_PARITY 0
#define XPAR_RS232_UART_1_ODD_PARITY 0
#define XPAR_RS232_UART_1_DATA_BITS 8
/******************************************************************/
#define XPAR_XSYSACE_MEM_WIDTH 8
#define XPAR_XSYSACE_NUM_INSTANCES 1
#define XPAR_SYSACE_COMPACTFLASH_BASEADDR 0x41800000
#define XPAR_SYSACE_COMPACTFLASH_HIGHADDR 0x4180FFFF
#define XPAR_SYSACE_COMPACTFLASH_DEVICE_ID 0
#define XPAR_SYSACE_COMPACTFLASH_MEM_WIDTH 8
/******************************************************************/
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 3
#define XPAR_XINTC_HAS_IPR 1
#define XPAR_XINTC_USE_DCR 0
#define XPAR_XINTC_NUM_INSTANCES 1
#define XPAR_OPB_INTC_0_BASEADDR 0x41200000
#define XPAR_OPB_INTC_0_HIGHADDR 0x4120FFFF
#define XPAR_OPB_INTC_0_DEVICE_ID 0
#define XPAR_OPB_INTC_0_KIND_OF_INTR 0x00000006
/******************************************************************/
#define XPAR_INTC_SINGLE_BASEADDR 0x41200000
#define XPAR_INTC_SINGLE_HIGHADDR 0x4120FFFF
#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID
#define XPAR_SYSACE_COMPACTFLASH_SYSACE_IRQ_MASK 0X000001
#define XPAR_OPB_INTC_0_SYSACE_COMPACTFLASH_SYSACE_IRQ_INTR 0
#define XPAR_RS232_UART_1_INTERRUPT_MASK 0X000002
#define XPAR_OPB_INTC_0_RS232_UART_1_INTERRUPT_INTR 1
#define XPAR_DDR_SDRAM_32MX32_IP2INTC_IRPT_MASK 0X000004
#define XPAR_OPB_INTC_0_DDR_SDRAM_32MX32_IP2INTC_IRPT_INTR 2
/******************************************************************/
#define XPAR_XDDR_NUM_INSTANCES 1
#define XPAR_DDR_SDRAM_32MX32_ECC_BASEADDR 0xFFFFFFFF
#define XPAR_DDR_SDRAM_32MX32_ECC_HIGHADDR 0x00000000
#define XPAR_DDR_SDRAM_32MX32_DEVICE_ID 0
#define XPAR_DDR_SDRAM_32MX32_INCLUDE_ECC_INTR 0
/******************************************************************/
#define XPAR_DDR_SDRAM_32MX32_MEM0_BASEADDR 0x00000000
#define XPAR_DDR_SDRAM_32MX32_MEM0_HIGHADDR 0x07FFFFFF
/******************************************************************/
#define XPAR_PLB_BRAM_IF_CNTLR_1_BASEADDR 0xffffc000
#define XPAR_PLB_BRAM_IF_CNTLR_1_HIGHADDR 0xffffffff
/******************************************************************/
#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000
/******************************************************************/
/******************************************************************/
/* Linux Redefines */
/******************************************************************/
#define XPAR_UARTLITE_0_BASEADDR XPAR_RS232_UART_1_BASEADDR
#define XPAR_UARTLITE_0_HIGHADDR XPAR_RS232_UART_1_HIGHADDR
#define XPAR_UARTLITE_0_DEVICE_ID XPAR_RS232_UART_1_DEVICE_ID
/******************************************************************/
#define XPAR_SYSACE_0_BASEADDR XPAR_SYSACE_COMPACTFLASH_BASEADDR
#define XPAR_SYSACE_0_HIGHADDR XPAR_SYSACE_COMPACTFLASH_HIGHADDR
#define XPAR_SYSACE_0_DEVICE_ID XPAR_SYSACE_COMP8CTFLASH_DEVICE_ID
/******************************************************************/
#define XPAR_INTC_0_BASEADDR XPAR_OPB_INTC_0_BASEADDR
#define XPAR_INTC_0_HIGHADDR XPAR_OPB_INTC_0_HIGHADDR
#define XPAR_INTC_0_KIND_OF_INTR XPAR_OPB_INTC_0_KIND_OF_INTR
#define XPAR_INTC_0_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID
/******************************************************************/
#define XPAR_INTC_0_SYSACE_0_VEC_ID XPAR_OPB_INTC_0_SYSACE_COMPACTFLASH_SYSACE_IRQ_INTR
#define XPAR_INTC_0_UARTLITE_0_VEC_ID XPAR_OPB_INTC_0_RS232_UART_1_INTERRUPT_INTR
#define XPAR_INTC_0_DDR_0_VEC_ID XPAR_OPB_INTC_0_DDR_SDRAM_32MX32_IP2INTC_IRPT_INTR
/******************************************************************/
#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
#define XPAR_CORE_CLOCK_FREQ_HZ XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ
#define XPAR_DDR_0_SIZE 8000000
/******************************************************************/
#define XPAR_PERSISTENT_0_IIC_0_BASEADDR 0x00000400
#define XPAR_PERSISTENT_0_IIC_0_HIGHADDR 0x000007FF
#define XPAR_PERSISTENT_0_IIC_0_EEPROMADDR 0xA0
/******************************************************************/
#define XPAR_PCI_0_CLOCK_FREQ_HZ 0
/******************************************************************/
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