bug in arch/ppc/boot/common/util.S: cmplwi cr0,r3,r4 ?
Frank van Maarseveen
frankvm at frankvm.com
Wed Aug 3 23:18:48 EST 2005
I think "cmplwi" expects an immediate vale as last operand
around line 255 of arch/ppc/boot/common/util.S:
addi r4,r4,_etext at l # r8 = &_etext
1: dcbf r0,r3 # Flush the data cache
icbi r0,r3 # Invalidate the instruction cache
addi r3,r3,0x10 # Increment by one cache line
cmplwi cr0,r3,r4 # Are we at the end yet?
blt 1b # No, keep flushing and invalidating
I guess it should have been:
cmplw cr0,r3,r4 # Are we at the end yet?
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