early UART mapping in head_44x.S

Ralph Siemsen rsiemsen at rossvideo.com
Wed Jul 14 08:48:37 EST 2004

James Perkins wrote:

> ori won't clear the invalid bits, it just "or"s in the TS bit itself.
> What suprises me is that TLB 1 is being written twice. It may make more
> sense to change the second case
>         li      r0,1            /* TLB slot 1 */
> to
>        li      r0,2             /* TLB slot 2 */
> So that there is both a TS=0 and a TS=1 mapping, in TLB entry index 1
> and 2, respectively -- this will catch both the MSR[DS]=0 and MSR[DS]=1
> cases.

Yes I see now.  Your suggestion also works, and it seems more logical -
though I doubt anything in the early startup would ever do an access in
TS=1 virtual space... shortly after this the real MMU init is done and
it will overwrite all of these temporary mappings...


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