early UART mapping in head_44x.S
rsiemsen at rossvideo.com
Wed Jul 14 07:51:47 EST 2004
Ralph Siemsen wrote:
> Can anyone explain how this is meant to work? Specifically, the
> ori r3,r3,PPC44x_TLB_TS
> would clear the other bits in this register, including the "valid" bit,
> so how is this mapping supposed to work?
Clearly demonstrating that I have been staring that this line of code
too long... the ori instruction sets the TS bit and shouldn't affect the
However, if I dump the TLB entry after the isync using the BDI
interface, it shows the EPN is zero'd out:
IDX TID EPN SIZE VTS RPN USER WIMGE USRSVC
1 : 00 00000000 1KB -0 -> 1_40000000 U:0000 -I-G- -WR-WR
whereas without the second "tlbwe" instructions, I get the expected and
1 : 00 e0000000 256MB V0 -> 1_40000000 U:0000 -I-G- ----WR
What's the secret?
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