[PATCH] Workaround for 745x data corruption bug

[Brian Waite]

Ben,

So what kind of aliasing issues do you forsee uner 2.4?
Thanks
Brian
On Wed, 04 Aug 2004 10:45:32 +1000, Benjamin Herrenschmidt
<benh at kernel.crashing.org> wrote:
>
> > Looking at this errata, I don't think poeple using Marvell chips will
> > be affected by this errata.
> > I don't see this as impacting the IO subsystem only the internal MPX system. IE
> > using a 2 74xx system and not using the M bit. This race can also
> > occur on a single processor system with the M disabled, as it is in
> > Linux, but it has nothing to do with the memory controller mapping its
> > PCI<->mem windows as non cacheable. You should be able to boost the IO
> > throughput using non coherency without this errata impacting you any
> > more than it already is.
> >
> > Anyone please correct me if I am wrong because I need to know.
>
> Note that I feel obligated to re-state again that doing non-coherent
> DMA on a 6xx/7xx/7xxx CPU is a big no brainer and is asking for all sorts
> of cache aliasing issues because of the way the kernel linear mapping of
> memory is BAT mapped... (Note that 2.6 should be able to deal with the
> DBAT beeing disabled, at the expense of perfs, though I'm pretty sure we
> need the IBAT still set).
>
> Ben.
>
>

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