confused about HID1 bits and G5
cfriesen at nortelnetworks.com
Thu Apr 29 03:36:54 EST 2004
I'm looking at 2.6.5, in the setup for the G5, specifically the HID1 register.
According to the docs for the chip, the default setting is all zeros, and the preferred setting is
The only place I see HID1 being set is in __power4_cpu_preinit, and it executes the following:
li r11,0x1200 /* enable i-fetch cacheability */
sldi r11,r11,44 /* and prefetch */
It appears that we're relying on the firmware to set up a lot of the bits in this register--is there
any reason we aren't forcing particular values?
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