cache coherence problem

[Benjamin Herrenschmidt]

>  newly mapped in blank pages,
>
> If you mean zeroed pages for blanked, I believe that it is wrong.
> The reason being that 0 is an invalid instruction so that the code
> would trap in any case.
>
> Maybe I'm wrong, but I seem to remember this as an optimization
> that Paulus implemented some time ago.

And that we had to undo because glibc relied on it, not invalidating
cache lines in some conditions assuming newly mapped zeroed pages
are delivered icache-clean by the kernel.

One of the arguments of the glibc folks for not fixing that was that
it would be a security hole to let stale icache content leak, so the
kernel has to invalidate them anyway.

Ben.

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