"Illegal instruction" traps on smp clients - 2.4.19

[Michael R. Zucca]

David Bryan wrote:
 > These modes are controlled by two bits in
> the Memory subsystem control register (MSSCR0).  At reset, the MSSCR0
> defaults to MEI mode with the SHD signal disabled.  By placing the 7400 in
> MESI mode at boot, we solved the problem.

Would you care to share what MSSCR0 bits these were and what you set
them to? :-)

--
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  Michael Zucca - mrz5149 at acm.org
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  "I'm too old to use Emacs." -- Rod MacDonald
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