"Illegal instruction" traps on smp clients - 2.4.19

Michael R. Zucca mrz5149 at acm.org
Fri Feb 28 05:26:22 EST 2003

David Bryan wrote:
 > These modes are controlled by two bits in
> the Memory subsystem control register (MSSCR0).  At reset, the MSSCR0
> defaults to MEI mode with the SHD signal disabled.  By placing the 7400 in
> MESI mode at boot, we solved the problem.

Would you care to share what MSSCR0 bits these were and what you set
them to? :-)

  Michael Zucca - mrz5149 at acm.org
  "I'm too old to use Emacs." -- Rod MacDonald

** Sent via the linuxppc-dev mail list. See http://lists.linuxppc.org/

More information about the Linuxppc-dev mailing list