ghannon at cspi.com ghannon at cspi.com
Sat Dec 14 07:51:57 EST 2002

We are developing a custom 74xx based board with a gt64260b.
On board is a device we are acessing through pci0 on the gt64260b.

I've noticed that in the device's configuration header, the cache line
size parameter is not what I want it to be.   Is pcibios_fixup the
place in the kernel to make such a change?
(that is in my specific platform_setup.c file)
Or, should I do it in the
driver that uses that device?

Thanks for any direction.

Gary Hannon
ghannon at cspi.com

** Sent via the linuxppc-dev mail list. See http://lists.linuxppc.org/

More information about the Linuxppc-dev mailing list