L1 & L2 cache guidelines

[jlhagen at rockwellcollins.com]

Hello,

we are working with the IBM 750cxe processor and it has both an L1 and L2
cache. We are cutting our teeth on this stuff and we are wondering about
handling cache operations between the two. Are there general things that
shouldn't be done? Good practices? Any hints etc... would be appreciated.

Thanks,
John


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