ppc LE questions (seeking help hand info pointers)

[Albert D. Cahalan]

Dan Malek writes:

> Another technical reason is as the processor family moves forward,
> less and less little endian support is provided. In the case of
> the 7450, there are instructions that trap to the kernel to be
> emulated in LE mode, that are executed in the core in BE mode.

Quit spreading FUD. The 7450 has _better_ LE support than the 7400
and 7410 did. With the 7450, misaligned LE memory operations now
perform just as well as misaligned BE memory operations.

I checked the errata too. Total BE/LE differences I found:


1. TLBMISS always has a BE address. Motorola's example code for
   software TLB reloads has a "xori" instruction to deal with this.

2. No string/multi load/store instructions in LE mode.
   According to Motorola's 32-bit arch book, these instructions
   are expected to be slow anyway. (They sure aren't RISC!)
   Indeed, the 7450 doesn't handle them well even in BE mode.

3. The MPC106 chip ("Grackle" host bridge) won't work.

4. The MPC107 chip (another host bridge) won't tolerate unaligned data.

5. LE mode enables address munging. :-)

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