floating-point under ppc/linux
hobold at Informatik.Uni-Bremen.DE
Wed Oct 31 01:50:29 EST 2001
Gary Byers <gb at gse.com> writes:
> Note that some PPC implementations (e.g., the 750) consider any
> combination of the FE0/FE1 bits other than 00 to imply precise mode;
> it seems like "precise" and "disabled" are the only modes that can be
> portably supported. I don't what considerations led the 750's
> designers to make this change and don't know whether it's a trend or
> an isolated case.
I'd hazard a guess that imprecise floating point exceptions will be
slowly phased out of modern Out-Of-Order RISCs.
In the 750 (and the whole family line from 603 to 7450), there would be
no speed gain from allowing FP exceptions to be signalled imprecisely.
Precise exceptions are basically "free" once you have a queue which enables
you to complete instructions in program order, because you can also do
checking for exceptions in program order.
(Well, there would be a small gain with imprecise FP exceptions because
you wouldn't need to track them in the queue. But in practice you run out
of other resources before you run out of completion queue entries.)
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