Mac nVidia GeForce2 support patches
Ani Joshi
ajoshi at shell.unixbox.com
Mon Oct 8 15:36:57 EST 2001
Attatched is a patch which should apply to any recent 2.4 tree's
drivers/video/riva directory. This adds ppc/general big-endian support
for nVidia boards, and supports the GeForce2 MX found in Apple's new
machines. The rivafb driver currently does not support the GeForce3 so if
you Mac has that then you'll have to wait a bit, don't bother trying this
patch.
Also attatched is a patch against XFree86 4.1.0 which adds above stated
support to the nv driver, GeForce3 is supported in this driver.
Feedback and bugreports are welcome, cc me any replies as I am not on most
of these lists.
Special thanks to Dan Burcaw and the rest of the Terra Soft team for
providing me the hardware allowing me to do this work.
ani
-------------- next part --------------
diff -uNr riva.orig/fbdev.c riva/fbdev.c
--- riva.orig/fbdev.c Mon Sep 24 23:33:05 2001
+++ riva/fbdev.c Tue Sep 25 01:10:18 2001
@@ -95,7 +95,11 @@
#define CURSOR_HIDE_DELAY (20)
#define CURSOR_SHOW_DELAY (3)
+#ifdef __BIG_ENDIAN
+#define CURSOR_COLOR 0xff7f
+#else
#define CURSOR_COLOR 0x7fff
+#endif
#define TRANSPARENT_COLOR 0x0000
#define MAX_CURS 32
@@ -251,7 +255,7 @@
/* command line data, set in rivafb_setup() */
static char fontname[40] __initdata = { 0 };
-static char noaccel __initdata = 0;
+static char noaccel __initdata = 1;
static char nomove = 0;
static char nohwcursor __initdata = 0;
static char noblink = 0;
@@ -1212,6 +1216,10 @@
if (regno >= riva_get_cmap_len(&p->var))
return -EINVAL;
+ red >>= 8;
+ green >>= 8;
+ blue >>= 8;
+
rivainfo->palette[regno].red = red;
rivainfo->palette[regno].green = green;
rivainfo->palette[regno].blue = blue;
@@ -1226,7 +1234,11 @@
#ifdef FBCON_HAS_CFB8
case 8:
/* "transparent" stuff is completely ignored. */
+#if 0
riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
+#else
+ riva_wclut(chip, regno, red, green, blue);
+#endif
break;
#endif /* FBCON_HAS_CFB8 */
#ifdef FBCON_HAS_CFB16
@@ -1863,6 +1875,15 @@
assert(rinfo->base0_region_size >= 0x00800000); /* from GGI */
assert(rinfo->base1_region_size >= 0x01000000); /* from GGI */
+
+ {
+ /* enable IO and mem */
+ unsigned short cmd;
+
+ pci_read_config_word(pd, PCI_COMMAND, &cmd);
+ cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
+ pci_write_config_word(pd, PCI_COMMAND, cmd);
+ }
rinfo->ctrl_base_phys = pci_resource_start(rinfo->pd, 0);
rinfo->fb_base_phys = pci_resource_start(rinfo->pd, 1);
diff -uNr riva.orig/riva_hw.c riva/riva_hw.c
--- riva.orig/riva_hw.c Mon Sep 24 23:33:05 2001
+++ riva/riva_hw.c Mon Sep 24 23:36:01 2001
@@ -1890,6 +1890,9 @@
RIVA_HW_INST *chip
)
{
+#if defined(__BIG_ENDIAN)
+ chip->PMC[0x00000004/4] = 0x01000001;
+#endif
/*
* Fill in chip configuration.
*/
diff -uNr riva.orig/riva_hw.h riva/riva_hw.h
--- riva.orig/riva_hw.h Mon Sep 24 23:33:05 2001
+++ riva/riva_hw.h Mon Sep 24 23:59:10 2001
@@ -59,8 +59,14 @@
/*
* HW access macros.
*/
+#if defined(__powerpc__)
+#include <asm/io.h>
+#define NV_WR08(p,i,d) out_8(p+i, d)
+#define NV_RD08(p,i) in_8(p+i)
+#else
#define NV_WR08(p,i,d) (((U008 *)(p))[i]=(d))
#define NV_RD08(p,i) (((U008 *)(p))[i])
+#endif
#define NV_WR16(p,i,d) (((U016 *)(p))[(i)/2]=(d))
#define NV_RD16(p,i) (((U016 *)(p))[(i)/2])
#define NV_WR32(p,i,d) (((U032 *)(p))[(i)/4]=(d))
@@ -86,8 +92,12 @@
typedef volatile struct
{
U032 reserved00[4];
+#ifdef __BIG_ENDIAN
+ U032 FifoFree;
+#else
U016 FifoFree;
U016 Nop;
+#endif
U032 reserved01[0x0BB];
U032 Rop3;
} RivaRop;
@@ -97,8 +107,12 @@
typedef volatile struct
{
U032 reserved00[4];
+#ifdef __BIG_ENDIAN
+ U032 FifoFree;
+#else
U016 FifoFree;
U016 Nop;
+#endif
U032 reserved01[0x0BD];
U032 Shape;
U032 reserved03[0x001];
@@ -112,8 +126,12 @@
typedef volatile struct
{
U032 reserved00[4];
+#ifdef __BIG_ENDIAN
+ U032 FifoFree;
+#else
U016 FifoFree;
U016 Nop;
+#endif
U032 reserved01[0x0BB];
U032 TopLeft;
U032 WidthHeight;
@@ -124,8 +142,12 @@
typedef volatile struct
{
U032 reserved00[4];
+#ifdef __BIG_ENDIAN
+ U032 FifoFree;
+#else
U016 FifoFree;
U016 Nop[1];
+#endif
U032 reserved01[0x0BC];
U032 Color;
U032 reserved03[0x03E];
@@ -138,8 +160,12 @@
typedef volatile struct
{
U032 reserved00[4];
+#ifdef __BIG_ENDIAN
+ U032 FifoFree;
+#else
U016 FifoFree;
U016 Nop;
+#endif
U032 reserved01[0x0BB];
U032 TopLeftSrc;
U032 TopLeftDst;
@@ -151,8 +177,12 @@
typedef volatile struct
{
U032 reserved00[4];
+#ifdef __BIG_ENDIAN
+ U032 FifoFree;
+#else
U016 FifoFree;
U016 Nop[1];
+#endif
U032 reserved01[0x0BC];
U032 TopLeft;
U032 WidthHeight;
@@ -166,8 +196,12 @@
typedef volatile struct
{
U032 reserved00[4];
+#ifdef __BIG_ENDIAN
+ U032 FifoFree;
+#else
U016 FifoFree;
U016 Nop;
+#endif
U032 reserved01[0x0BB];
U032 reserved03[(0x040)-1];
U032 Color1A;
@@ -228,8 +262,12 @@
typedef volatile struct
{
U032 reserved00[4];
+#ifdef __BIG_ENDIAN
+ U032 FifoFree;
+#else
U016 FifoFree;
U016 Nop;
+#endif
U032 reserved01[0x0BC];
U032 TextureOffset;
U032 TextureFormat;
@@ -254,8 +292,12 @@
typedef volatile struct
{
U032 reserved00[4];
+#ifdef __BIG_ENDIAN
+ U032 FifoFree;
+#else
U016 FifoFree;
U016 Nop;
+#endif
U032 reserved01[0x0BB];
U032 ColorKey;
U032 TextureOffset;
@@ -288,8 +330,12 @@
typedef volatile struct
{
U032 reserved00[4];
+#ifdef __BIG_ENDIAN
+ U032 FifoFree;
+#else
U016 FifoFree;
U016 Nop[1];
+#endif
U032 reserved01[0x0BC];
U032 Color; /* source color 0304-0307*/
U032 Reserved02[0x03e];
@@ -319,16 +365,24 @@
typedef volatile struct
{
U032 reserved00[4];
+#ifdef __BIG_ENDIAN
+ U032 FifoFree;
+#else
U016 FifoFree;
U016 Nop;
+#endif
U032 reserved01[0x0BE];
U032 Offset;
} RivaSurface;
typedef volatile struct
{
U032 reserved00[4];
+#ifdef __BIG_ENDIAN
+ U032 FifoFree;
+#else
U016 FifoFree;
U016 Nop;
+#endif
U032 reserved01[0x0BD];
U032 Pitch;
U032 RenderBufferOffset;
diff -uNr riva.orig/riva_tbl.h riva/riva_tbl.h
--- riva.orig/riva_tbl.h Mon Sep 24 23:33:05 2001
+++ riva/riva_tbl.h Mon Sep 24 23:53:14 2001
@@ -830,29 +830,45 @@
{0x00000501, 0x01FFFFFF},
{0x00000502, 0x00000002},
{0x00000503, 0x00000002},
+#ifdef __BIG_ENDIAN
+ {0x00000508, 0x01088043},
+#else
{0x00000508, 0x01008043},
+#endif
{0x0000050A, 0x00000000},
{0x0000050B, 0x00000000},
+#ifdef __BIG_ENDIAN
+ {0x0000050C, 0x01088019},
+#else
{0x0000050C, 0x01008019},
+#endif
{0x0000050E, 0x00000000},
{0x0000050F, 0x00000000},
-#if 1
- {0x00000510, 0x01008018},
+#ifdef __BIG_ENDIAN
+ {0x00000510, 0x01088018},
#else
- {0x00000510, 0x01008044},
+ {0x00000510, 0x01008018},
#endif
{0x00000512, 0x00000000},
{0x00000513, 0x00000000},
+#ifdef __BIG_ENDIAN
+ {0x00000514, 0x01088021},
+#else
{0x00000514, 0x01008021},
+#endif
{0x00000516, 0x00000000},
{0x00000517, 0x00000000},
+#ifdef __BIG_ENDIAN
+ {0x00000518, 0x0108805F},
+#else
{0x00000518, 0x0100805F},
+#endif
{0x0000051A, 0x00000000},
{0x0000051B, 0x00000000},
-#if 1
- {0x0000051C, 0x0100804B},
+#ifdef __BIG_ENDIAN
+ {0x0000051C, 0x0108804B},
#else
- {0x0000051C, 0x0100804A},
+ {0x0000051C, 0x0100804B},
#endif
{0x0000051E, 0x00000000},
{0x0000051F, 0x00000000},
@@ -868,10 +884,18 @@
{0x00000529, 0x00000D01},
{0x0000052A, 0x11401140},
{0x0000052B, 0x00000000},
+#ifdef __BIG_ENDIAN
+ {0x0000052C, 0x00080058},
+#else
{0x0000052C, 0x00000058},
+#endif
{0x0000052E, 0x11401140},
{0x0000052F, 0x00000000},
+#ifdef __BIG_ENDIAN
+ {0x00000530, 0x00080059},
+#else
{0x00000530, 0x00000059},
+#endif
{0x00000532, 0x11401140},
{0x00000533, 0x00000000},
{0x00000534, 0x0000005A},
@@ -882,7 +906,14 @@
{0x0000053B, 0x00000000},
{0x0000053C, 0x00000093},
{0x0000053E, 0x11401140},
- {0x0000053F, 0x00000000}
+ {0x0000053F, 0x00000000},
+#ifdef __BIG_ENDIAN
+ {0x00000540, 0x0308A01C},
+#else
+ {0x00000540, 0x0300A01C},
+#endif
+ {0x00000542, 0x11401140},
+ {0x00000543, 0x00000000}
};
static unsigned nv10TablePRAMIN_8BPP[][2] =
{
@@ -898,7 +929,8 @@
{0x0000052E, 0x00000302},
{0x00000535, 0x00000000},
{0x00000539, 0x00000000},
- {0x0000053D, 0x00000000}
+ {0x0000053D, 0x00000000},
+ {0x00000541, 0x00000302}
};
static unsigned nv10TablePRAMIN_15BPP[][2] =
{
@@ -914,7 +946,8 @@
{0x0000052E, 0x00000902},
{0x00000535, 0x00000902},
{0x00000539, 0x00000902},
- {0x0000053D, 0x00000902}
+ {0x0000053D, 0x00000902},
+ {0x00000541, 0x00000902}
};
static unsigned nv10TablePRAMIN_16BPP[][2] =
{
@@ -930,7 +963,8 @@
{0x0000052E, 0x00000C02},
{0x00000535, 0x00000C02},
{0x00000539, 0x00000C02},
- {0x0000053D, 0x00000C02}
+ {0x0000053D, 0x00000C02},
+ {0x00000541, 0x00000C02}
};
static unsigned nv10TablePRAMIN_32BPP[][2] =
{
@@ -946,6 +980,7 @@
{0x0000052E, 0x00000E02},
{0x00000535, 0x00000E02},
{0x00000539, 0x00000E02},
- {0x0000053D, 0x00000E02}
+ {0x0000053D, 0x00000E02},
+ {0x00000541, 0x00000E02}
};
-------------- next part --------------
diff -uNr nv.orig/nv_driver.c nv/nv_driver.c
--- nv.orig/nv_driver.c Sun Oct 7 22:28:30 2001
+++ nv/nv_driver.c Sun Oct 7 22:28:35 2001
@@ -885,7 +885,7 @@
pNv->Primary = xf86IsPrimaryPci(pNv->PciInfo);
-#ifndef __alpha__
+#if !defined(__alpha__) || !defined(__powerpc__)
/* Initialize the card through int10 interface if needed */
#if 0
if ( !pNv->Primary &&)
@@ -1280,9 +1280,9 @@
pNv->FbMapSize = pScrn->videoRam * 1024;
+#if 0
/* Read and print the Monitor DDC info */
pScrn->monitor->DDC = NVdoDDC(pScrn);
-#if 0
/*
* This code was for testing. It will be removed as soon
* as this is integrated into the common level.
@@ -1610,6 +1610,18 @@
if ( pNv->Restore )
(*pNv->Restore)(pScrn, vgaReg, nvReg, FALSE);
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ /* turn on LFB swapping */
+ {
+ unsigned char tmp;
+
+ VGA_WR08(pNv->riva.PCIO, 0x3d4, 0x46);
+ tmp = VGA_RD08(pNv->riva.PCIO, 0x3d5);
+ tmp |= (1 << 7);
+ VGA_WR08(pNv->riva.PCIO, 0x3d5, tmp);
+ }
+#endif
+
NVResetGraphics(pScrn);
vgaHWProtect(pScrn, FALSE);
@@ -1933,7 +1945,14 @@
vgaRegPtr vgaReg = &pVga->SavedReg;
DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "NVSave\n"));
+#if defined(__powerpc__)
+ /* temporary hack to get around PowerMac's inability to save
+ * vga fonts and cmap, will find a better solution later
+ */
+ vgaHWSave(pScrn, vgaReg, VGA_SR_MODE);
+#else
vgaHWSave(pScrn, vgaReg, VGA_SR_CMAP|VGA_SR_MODE|VGA_SR_FONTS);
+#endif
pNv->riva.UnloadStateExt(&pNv->riva, nvReg);
}
diff -uNr nv.orig/nv_xaa.c nv/nv_xaa.c
--- nv.orig/nv_xaa.c Sun Oct 7 22:28:30 2001
+++ nv/nv_xaa.c Sun Oct 7 22:28:35 2001
@@ -596,8 +596,12 @@
NVSubsequentMono8x8PatternFillRect;
/* Color expansion */
- infoPtr->ScanlineCPUToScreenColorExpandFillFlags =
+ infoPtr->ScanlineCPUToScreenColorExpandFillFlags =
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ BIT_ORDER_IN_BYTE_MSBFIRST |
+#else
BIT_ORDER_IN_BYTE_LSBFIRST |
+#endif
NO_PLANEMASK |
CPU_TRANSFER_PAD_DWORD |
LEFT_EDGE_CLIPPING |
diff -uNr nv.orig/riva_hw.c nv/riva_hw.c
--- nv.orig/riva_hw.c Sun Oct 7 22:28:30 2001
+++ nv/riva_hw.c Sun Oct 7 22:28:35 2001
@@ -1656,6 +1656,11 @@
int pan = (start & 3) << 1;
unsigned char tmp;
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ /* turn on big endian register access */
+ chip->PMC[0x00000004/4] = 0x01000001;
+#endif
+
/*
* Unlock extended registers.
*/
diff -uNr nv.orig/riva_hw.h nv/riva_hw.h
--- nv.orig/riva_hw.h Sun Oct 7 22:28:30 2001
+++ nv/riva_hw.h Sun Oct 7 22:28:35 2001
@@ -60,8 +60,12 @@
typedef volatile struct
{
U032 reserved00[4];
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ U032 FifoFree;
+#else
U016 FifoFree;
U016 Nop;
+#endif
U032 reserved01[0x0BB];
U032 Rop3;
} RivaRop;
@@ -71,8 +75,12 @@
typedef volatile struct
{
U032 reserved00[4];
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ U032 FifoFree;
+#else
U016 FifoFree;
U016 Nop;
+#endif
U032 reserved01[0x0BD];
U032 Shape;
U032 reserved03[0x001];
@@ -86,8 +94,12 @@
typedef volatile struct
{
U032 reserved00[4];
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ U032 FifoFree;
+#else
U016 FifoFree;
U016 Nop;
+#endif
U032 reserved01[0x0BB];
U032 TopLeft;
U032 WidthHeight;
@@ -98,8 +110,12 @@
typedef volatile struct
{
U032 reserved00[4];
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ U032 FifoFree;
+#else
U016 FifoFree;
U016 Nop[1];
+#endif
U032 reserved01[0x0BC];
U032 Color;
U032 reserved03[0x03E];
@@ -112,8 +128,12 @@
typedef volatile struct
{
U032 reserved00[4];
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ U032 FifoFree;
+#else
U016 FifoFree;
U016 Nop;
+#endif
U032 reserved01[0x0BB];
U032 TopLeftSrc;
U032 TopLeftDst;
@@ -125,8 +145,12 @@
typedef volatile struct
{
U032 reserved00[4];
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ U032 FifoFree;
+#else
U016 FifoFree;
U016 Nop[1];
+#endif
U032 reserved01[0x0BC];
U032 TopLeft;
U032 WidthHeight;
@@ -140,8 +164,12 @@
typedef volatile struct
{
U032 reserved00[4];
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ U032 FifoFree;
+#else
U016 FifoFree;
U016 Nop;
+#endif
U032 reserved01[0x0BB];
U032 reserved03[(0x040)-1];
U032 Color1A;
@@ -202,8 +230,12 @@
typedef volatile struct
{
U032 reserved00[4];
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ U032 FifoFree;
+#else
U016 FifoFree;
U016 Nop;
+#endif
U032 reserved01[0x0BC];
U032 TextureOffset;
U032 TextureFormat;
@@ -228,8 +260,12 @@
typedef volatile struct
{
U032 reserved00[4];
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ U032 FifoFree;
+#else
U016 FifoFree;
U016 Nop;
+#endif
U032 reserved01[0x0BB];
U032 ColorKey;
U032 TextureOffset;
@@ -262,8 +298,12 @@
typedef volatile struct
{
U032 reserved00[4];
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ U032 FifoFree;
+#else
U016 FifoFree;
U016 Nop[1];
+#endif
U032 reserved01[0x0BC];
U032 Color; /* source color 0304-0307*/
U032 Reserved02[0x03e];
@@ -293,16 +333,24 @@
typedef volatile struct
{
U032 reserved00[4];
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ U032 FifoFree;
+#else
U016 FifoFree;
U016 Nop;
+#endif
U032 reserved01[0x0BE];
U032 Offset;
} RivaSurface;
typedef volatile struct
{
U032 reserved00[4];
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ U032 FifoFree;
+#else
U016 FifoFree;
U016 Nop;
+#endif
U032 reserved01[0x0BD];
U032 Pitch;
U032 RenderBufferOffset;
diff -uNr nv.orig/riva_tbl.h nv/riva_tbl.h
--- nv.orig/riva_tbl.h Sun Oct 7 22:28:30 2001
+++ nv/riva_tbl.h Sun Oct 7 22:28:35 2001
@@ -844,29 +844,45 @@
{0x00000501, 0x01FFFFFF},
{0x00000502, 0x00000002},
{0x00000503, 0x00000002},
- {0x00000508, 0x01008043},
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ {0x00000508, 0x01088043},
+#else
+ {0x00000508, 0x01008043},
+#endif
{0x0000050A, 0x00000000},
{0x0000050B, 0x00000000},
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ {0x0000050C, 0x01088019},
+#else
{0x0000050C, 0x01008019},
+#endif
{0x0000050E, 0x00000000},
{0x0000050F, 0x00000000},
-#if 1
- {0x00000510, 0x01008018},
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ {0x00000510, 0x01088018},
#else
- {0x00000510, 0x01008044},
+ {0x00000510, 0x01008018},
#endif
{0x00000512, 0x00000000},
{0x00000513, 0x00000000},
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ {0x00000514, 0x01088021},
+#else
{0x00000514, 0x01008021},
+#endif
{0x00000516, 0x00000000},
{0x00000517, 0x00000000},
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ {0x00000518, 0x0108805F},
+#else
{0x00000518, 0x0100805F},
+#endif
{0x0000051A, 0x00000000},
{0x0000051B, 0x00000000},
-#if 1
- {0x0000051C, 0x0100804B},
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ {0x0000051C, 0x0108804B},
#else
- {0x0000051C, 0x0100804A},
+ {0x0000051C, 0x0100804B},
#endif
{0x0000051E, 0x00000000},
{0x0000051F, 0x00000000},
@@ -882,10 +898,18 @@
{0x00000529, 0x00000D01},
{0x0000052A, 0x11401140},
{0x0000052B, 0x00000000},
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ {0x0000052C, 0x00080058},
+#else
{0x0000052C, 0x00000058},
+#endif
{0x0000052E, 0x11401140},
{0x0000052F, 0x00000000},
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ {0x00000530, 0x00080059},
+#else
{0x00000530, 0x00000059},
+#endif
{0x00000532, 0x11401140},
{0x00000533, 0x00000000},
{0x00000534, 0x0000005A},
@@ -897,7 +921,11 @@
{0x0000053C, 0x00000093},
{0x0000053E, 0x11401140},
{0x0000053F, 0x00000000},
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ {0x00000540, 0x0308A01C},
+#else
{0x00000540, 0x0300A01C},
+#endif
{0x00000542, 0x11401140},
{0x00000543, 0x00000000}
};
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