toe at unlserve.unl.edu
Wed Mar 28 09:35:31 EST 2001
On Tue, 27 Mar 2001, Iain Sandoe wrote:
> I wish I knew whether it would resume... it's not clear from the
> documentation I've got... (the IBM stuff).
It may be implementation dependent. MACE driver stops tx dma and resumes
afterwards, so tx side of dbdma on MACE must support it.
I have no idea if how AWACS' tx dbdma behaves, but it may be necessary to
make the write to control register multi-step or something, i.e., clear
RUN [in order to clear DEAD bit] and wait until RUN bit is cleared by hw,
then set RUN|WAKE..
> If it would, then we could save all this hassle completely...
> BTW: I don't *think* it does because one of my testers tried a similar
> method to the one you proposed and said it chopped up/repeated sound.
Hmm, I think it has to be either "chopped up" or "repeated" not both.. As
far as dbdma is concerned, those two are quite different effects.
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