7450 bugs & fixes
Timothy A. Seufert
tas at mindspring.com
Sat Dec 15 07:41:52 EST 2001
At 8:19 PM +0100 12/14/01, Benjamin Herrenschmidt wrote:
>I don't neither, they didn't give me any detail. Could they catch
>icache misses on the bus and delay incoming tlbie (freezing the emitter)
>when that happen ? I don't know the bus protocol ...
Take this with a grain of salt (*), but I don't recall anything in
the bus protocol which could be used to identify whether a particular
busrt is filling an icache or a dcache miss, much less whether it's
an icache miss which happened during a tablewalk. It all looks the
same to the outside world.
(*) I've designed hardware, but it was a 750cx and 8260 system and
therefore plain old 60x bus, not MAXbus like the systems in question.
Also, I wasn't the one who had to get deep into the the 60x bus
protocol. That said, I don't remember anything in 60x which could
identify *why* a transfer was happening, and whenever I've skimmed
over MAXbus docs it looks a lot like a better version of 60x.
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