I-cache flushing on the 7400
paubert at iram.es
Sun Apr 1 03:51:55 EST 2001
On Sat, 31 Mar 2001, Samuel Rydh wrote:
> I recently discovered that the following sequence
> LI_PHYS( r2,split_store_patch )
> stw r4,0(r2) // store instruction
> dcbst 0,r2 // Flush cache
> icbi 0,r2
> .... some instructions and then a rfi to split_store_patch ....
> did not work properly on a G4s (but it did work flawlessly on my G3).
> To make the i-cache flush effective, I had to insert an extra
> 'sync' before the last isync. Consulting my Motorola manuals,
> the recommended sequence for the 7400 (but not for the 750) did have
> that extra sync. Looking at the 2.4.3-pre8 BK source, I discovered
> the 'sync' was sometimes missing (in flush_icache_range and in a
> few places in head.S). Shouldn't the sync really be added?
It should, while actually the isync does not seem necessary since rfi
is a context synchronizing instruction (rfi and sc include implicitly the
equivalent of an isync).
As a side note, this or something similar might have been the cause of a
recently reported problem with 7450 which crash when enabling MaxBUS but
work in traditional 60x bus mode. The reordering of bus operations which
takes place with maxbus makes this kind of bug much more likely to become
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