Trying to enable backside on a G4

[Guillaume Laurès]

Michel Lanners a écrit :

>
> Attached are actually two patches: the first one fixes the output of
> 'cat /proc/sys/kernel/l2cr', as it contains some errors and omissions.
> This part is only needed on 2.2.x and old 2.3.x kernels; it's integrated
> in 2.4.0-something.

Yes it is.

>
>
> The second patch adds command line functionality for 2.3/2.4 kernels.

Hum, it was included already in 2.4 from linuxcare.

I attached what gives a boot on my G4/8600 with "as it comes options in menuconfig" (exept for the
Adaptec stuff which I had to put in a module or I would still get forever
"SCSI host 2 channel 0 reset (pid 1942) timed out - trying harder
SCSI bus is being reset for host 2 channel 0."

What can I say :
l2cr seems not to be enabled, as confirms a cat /proc/... later
There is a conflict on the Adaptec 3940UW board which wasn't there on 2.2
There is still the "SCSI bus is being reset for host..." problem for the usable half of the card (may
be it's a firmware issue, I use the 4.1/AV firmaware)
eth0 and eth1 have been swapped, which is not cool since this box is may IP-Masqu box...

>
> I'll have to check whether all the steps I've taken to enable the cache
> are actually needed, since all the invalidate stuff should be handled by
> the function I'm calling. But it didn't work last I tried.... Once
> that's decided, I will resubmit the command line patch.

Taken from Motorola's G4 User's Manual is the following :

3.7.4 L2 Cache Initialization
Following a power-on or hard reset, the L2 cache and the L2 cache DLL are disabled
initially. Before enabling the L2 cache, the L2 cache DLL must first be configured through
the L2CR register, and the DLL must be allowed 640 L2 cache clock periods to achieve
phase lock. Before enabling the L2 cache, other configuration parameters must be set in the
L2CR, and the L2 cache tags must be globally invalidated. The L2 cache should be
initialized during system start-up.
The sequence for initializing the L2 cache is as follows:
1.  (automatically performed by the assertion of HRESET).
2. Disable L2 cache by clearing L2CR[L2E].
3. Set the L2CR[L2CLK] bits to the desired clock divider setting. Setting a nonzero
value automatically enables the DLL. All other L2 cache configuration bits should
be set to properly configure the L2 cache interface for the SRAM type, size, and
interface timing required.
4. Wait for the L2 cache DLL to achieve phase lock. This can be timed by setting the
decrementer for a time period equal to 640 L2 cache clocks, or by performing an L2
cache global invalidate.
5. Perform an L2 cache global invalidate. The global invalidate could be performed
before enabling the DLL, or in parallel with waiting for the DLL to stabilize. Refer
to Section 3.7.3.7, "L2 Cache Global Invalidation," for more information about L2
cache global invalidation. Note that a global invalidate always takes much longer
than it takes for the DLL to stabilize.
6. After the DLL stabilizes, an L2 cache global invalidate has been performed, and the
other L2 cache configuration bits have been set, enable the L2 cache for normal
operation by setting the L2CR[L2E] bit to 1.

So I attached a correct (I think) user-space script called L2BS_enable.sh which I'm going to
propagate on linuxppc-users, tell me what you think about. I will try to work on kernel space then.

I'm just unsure of the behaviour of :
while test 1 = $((`cat /proc/sys/kernel/l2cr | awk -F : '{print $1}'`&0x00000001)); do wait; done

I couldn't test this loop.

>
>
> > Since :
> >  - GrabG3CacheSetting (slightly modified to accept any processor or it would complain that I
> > don't have a G3...) from BenH told me that XLR8's extension sets my G4's L2CR to 0xb5100000
>
> Yeah, could you submit that back to Ben? I've noticed that as well when
> I started to play l2cr...

I did, but it's not good yet. Here is what I did :
Original code is :
[...]
if (cpuFamily != gestaltCPU750)
 {
  printf("Error, CPU is not a G3\n");
  exit(0);
 }
 printf ("Getting value of G3 L2CR register ...\n");
[...]

I put :
[...]
 if ((cpuFamily != gestaltCPU750) || (cpuFamily != gestaltCPU7400))
 {
  printf("Error, CPU is not a G3, nor a G4\n");
  exit(0);
 }
[...]
but it doesn't compile, so I had to comment out the whole test... Does anybody knows how to identify
a G4 under MacOS ?




Bye bye,


--
Guillaume

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