Altivec and binary compatibility

[Adrian Cox]

Giuliano Pochini wrote:
Giuliano Pochini wrote:

> > As the jmp_buf is a different size in Altivec and non-Altivec code
>
> Because with Altivec we need to save V registers, right ?  Well, I suppose
> intel developers had the same problem with P-III "vector" unit. How did they
> solve the problem ?

As far as I can tell, by ignoring it, and making the assumption that
only low-level libraries will use the vector registers.  I plan to take
a similar approach, and warn users not to mix Altivec and exceptions.

> > To add to the problem, throwing exceptions on an error is just what a
> > modern C++ library is supposed to do.  Throwing or catching an exception
> > in Altivec code will produce sequences that cannot execute on a G3
>
> Why ?? (sorry for my ignorance...)

I haven't studied GCC's implementation of exceptions in great detail.
The compiler saves and restores all the non-transient registers as part
of the exception sequence. When generating Altivec code this produces
stvx and lvx instructions, which will cause an illegal instruction
exception on G3 processors.

- Adrian Cox

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