allocating uncachable memory

[Ronald Wahl]

On Wed, 23 Aug 2000, Gabriel Paubert wrote:
> On Wed, 23 Aug 2000, Ronald Wahl wrote:
> > I'm writing a driver for a PCI controller in a PPC system. That driver
> > "exports" a bit of local ram into the PCI space. Now if some PCI device is
> > writing into this memory the local system won't notice it in all cases
>
> Yes, it will notice, unless there is a _serious_ bug in the host bridge.
> Accesses from the bridge to memory are snooped by the processor and the
> relevant cache lines are invalidated if necessary.
>
> The sequence is the following:
>
> - the PCI device requests the bus,
>
> - the PCI device becomes the master on the bus,
>
> - it puts an address and then data onto the (multiplexed) PCI bus,
>
> - the host bridge writes the data to system RAM at the specified address
> (beware of the difference between kernel, physical and PCI bus addresses),
> but before doing this the bridge signals the processor to invalidate or
> push to memory the corresponding cache lines.
>
> There is still a race with this kind of protocol: you need to read a
> register of you device in order to flush the buffers which might hold
> data on its way to memory in the host bridge.

What register? How do i flush the FIFOs of the PLX 9054? I played around
with the MARBR register but with no success so far. Maybe this register is
only used together with DMA but I need a flush mechanism that works w/o
DMA.

> Here is the code, guaranteed 100% bug-free ;-):
>
> ========================== CUT here ======================================
>
> ========================== CUT here ======================================

Haha. :-)

ron


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