question about altivec registers

[Tom Vier]

On Tue, Oct 26, 1999 at 08:22:06PM +0200, Geert Uytterhoeven wrote:

> Moving around blocks of 512 bytes quickly thrashes the L1 cache, unless the
> loads/stores are done using cache-bypassing instructions (cfr. MOVE16 on '040).
> Don't know whether PPC has these (still no PPC guru :-(

from what i've read, you can disable cache for the altivec regs. this was
intended for doing infrequent vector ops between frequent vectors ops
(loops) without distrubing the cache.

-- 
Tom Vier - 0x27371A1C
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