IRQ handling in port to DY4 SVME-177

[Charles Lepple]

Hi,
I'm working on porting the kernel to a DY4 SVME-177 board, a mil-spec 603e
single-board system (no PCI, nonstandard I/O, the works).

Anyway, the problem is with the interrupt controller, and it's more of an
architectural question. A Tundra SCV64 has several 'local IRQ' lines, but
as it turns out, they put all the useful stuff (serial, ethernet, SCSI) on
the same level IRQ level (LIRQ5). The RTC and other timers each get their
own IRQ level, as does the MAXpack interface. Is it probable that I can
get by with this sharing arrangement in arch/ppc/kernel/irq.c, or am I
going to have to create pseudo-IRQs for each device, and make it look like
a cascaded interrupt? The IRQ lines themselves are all level-sensitive,
but I'm wondering if the IRQ mask code in irq.c is going to be enough.
After all, am I losing anything but performance by using the same
interrupt line? (not that I would have designed it this way...)

--Charles Lepple                    |  Check one:
System Administrator                |    ( ) Routine matter
Virginia Tech EE Workstation Labs   |    ( ) Urgent
clepple at ee.vt.edu                   |    ( ) The future of the known 
http://www.ee.vt.edu/help/          |        universe hangs in the balance


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