bug in l2cr status display?

Michel Lanners mlan at cpu.lu
Fri Aug 27 07:05:40 EST 1999

Hi all,

While playing with the l2cr in order to set it manually after OF
booting, I've come across the following.

It seems that the effect of the L2CR[DO] bit isn't clear. In the 750
user manual, in the table describing l2cr, it says '... setting  this
bit enables the caching of instructions'. This doesn't corrsspond to
the name of the register, nor to what I see with my G3 upgrade card: in
normal operation, L2CR[DO] isn't set, but it makes no sense to disable
instruction caching excpet for test purposes.

So, what's happening? Is the user manual wrong? In that case, we should
correct arch/ppc/kernel/ppc_htab.c accordingly.

Any Motorola engineer around? Others with better docs? FWIW, I checked
the 750 errata already... nothing.


Michel Lanners                 |  " Read Philosophy.  Study Art.
23, Rue Paul Henkes            |    Ask Questions.  Make Mistakes.
L-1710 Luxembourg              |
email   mlan at cpu.lu            |
http://www.cpu.lu/~mlan        |                     Learn Always. "

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