[linux-fbdev] Re: readl() and friends and eieio on PPC

[Peter Chang]

I may have sent this too early during editing. Sorry if you've seen 
an incomplete one already.

At 10:13 +1000 08.12.1999, Paul Mackerras wrote:
>Richard Henderson <rth at cygnus.com> wrote:
>
> > There are a great many cards that do memory mapped i/o that don't care
> > about the ordering and write combining of the data setup, only that the
> > data setup all be done before receiving the "go code".  In these drivers,
> > we need only one wmb insn, not one between each and every writel.
> >
> > This benefit is marked enough that there is zero chance you can convince
>
>I'm curious to see the numbers.  What sort of driver do you see this
>much of an effect in?

When I did glide for the mac it definitely helped not do do an eieio 
after every pci write. The current generations of 3dfx hw use a sw 
managed fifo, and an eieio was only necessary when the sw layer 
needed to do do things to insert a 'barrier' in the fifo for later 
accounting.

>The only exceptions I can think of would be 3D graphics cards (and possibly
>also gigabit ethernet cards, although they should be doing most stuff
>by DMA).

Hmmm.... well the fifo in the 3dfx case lives on the board so there 
is a tradeoff of doing a lot of bus io and trying to make the 
rasterization responsive. Also the hw did not do dma, so this was 
sort of beside the point. :-)

\p

---
Underneath this flabby exterior is an enormous lack of character.
                     -- Oscar Levant

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