[PATCH 2/2] ARM: dts: aspeed: add Meta SanMiguel BMC
Potin Lai
potin.lai.pt at gmail.com
Wed Mar 11 19:05:33 AEDT 2026
On Mon, Feb 9, 2026 at 2:40 PM Andrew Jeffery
<andrew at codeconstruct.com.au> wrote:
>
> Hi Potin,
>
> Regarding the patch subject, can you please capitalise the start of the
> description after '... aspeed:'?
>
> ARM: dts: aspeed: Add Meta SanMiguel BMC
>
Hi Andrew,
Thank you for reminding.
Updated in v3.
> On Mon, 2026-02-02 at 14:03 +0800, Potin Lai wrote:
> > Add linux device tree entry for Meta (Facebook) SanMiguel compute-tray
> > BMC using AT2620 SoC.
> >
> > Signed-off-by: Potin Lai <potin.lai.pt at gmail.com>
> > ---
> > arch/arm/boot/dts/aspeed/Makefile | 1 +
> > .../dts/aspeed/aspeed-bmc-facebook-sanmiguel.dts | 1163 ++++++++++++++++++++
> > 2 files changed, 1164 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile
> > index 9adf9278dc94..ab2effc29f6f 100644
> > --- a/arch/arm/boot/dts/aspeed/Makefile
> > +++ b/arch/arm/boot/dts/aspeed/Makefile
> > @@ -30,6 +30,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
> > aspeed-bmc-facebook-harma.dtb \
> > aspeed-bmc-facebook-minerva.dtb \
> > aspeed-bmc-facebook-minipack.dtb \
> > + aspeed-bmc-facebook-sanmiguel.dtb \
> > aspeed-bmc-facebook-santabarbara.dtb \
> > aspeed-bmc-facebook-tiogapass.dtb \
> > aspeed-bmc-facebook-wedge40.dtb \
> > diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-sanmiguel.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-sanmiguel.dts
> > new file mode 100644
> > index 000000000000..bcf857835b23
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-sanmiguel.dts
> > @@ -0,0 +1,1163 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +// Copyright (c) 2025 Facebook Inc.
> > +
> > +/dts-v1/;
> > +#include "aspeed-g6.dtsi"
> > +#include <dt-bindings/gpio/aspeed-gpio.h>
> > +#include <dt-bindings/usb/pd.h>
> > +#include <dt-bindings/leds/leds-pca955x.h>
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/i2c/i2c.h>
> > +#include <dt-bindings/leds/common.h>
> > +
> > +/ {
> > + model = "AST2600 VR NVL144 BMC";
> > + compatible = "aspeed,ast2600";
>
> This is missing the platform compatible string defined in the previous
> patch.
>
Updated in v3.
> > +
> > + aliases {
> > + serial0 = &uart1;
> > + serial1 = &uart2;
> > + serial2 = &uart3;
> > + serial3 = &uart4;
> > + serial4 = &uart5;
> > + i2c16 = &imux16;
> > + i2c17 = &imux17;
> > + i2c18 = &imux18;
> > + i2c19 = &imux19;
> > + i2c20 = &i2c20;
> > + i2c21 = &i2c21;
> > + };
> > +
> > + chosen {
> > + stdout-path = "serial4:57600n8";
> > + };
> > +
> > + memory at 80000000 {
> > + device_type = "memory";
> > + reg = <0x80000000 0x80000000>;
> > + };
> > +
> > + iio-hwmon {
> > + compatible = "iio-hwmon";
> > + io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>,
> > + <&adc0 4>, <&adc0 5>, <&adc0 6>;
> > + };
> > +
> > + spi2_gpio: spi {
> > + compatible = "spi-gpio";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + sck-gpios = <&gpio0 ASPEED_GPIO(X, 3) GPIO_ACTIVE_HIGH>;
> > + mosi-gpios = <&gpio0 ASPEED_GPIO(X, 4) GPIO_ACTIVE_HIGH>;
> > + miso-gpios = <&gpio0 ASPEED_GPIO(X, 5) GPIO_ACTIVE_HIGH>;
> > + cs-gpios = <&gpio0 ASPEED_GPIO(X, 2) GPIO_ACTIVE_LOW>;
> > + num-chipselects = <1>;
> > +
> > + tpm at 0 {
> > + compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
> > + spi-max-frequency = <33000000>;
> > + reg = <0>;
> > + };
> > + };
> > +
> > + standby_power_regulator: standby-power-regulator {
> > + status = "okay";
> > + compatible = "regulator-fixed";
> > + regulator-name = "standby_power";
> > + gpio = <&gpio0 ASPEED_GPIO(M, 3) GPIO_ACTIVE_HIGH>;
> > + regulator-min-microvolt = <1800000>;
> > + regulator-max-microvolt = <1800000>;
> > + enable-active-high;
> > + regulator-always-on;
> > + regulator-boot-on;
> > + };
> > +
> > + scm-leds {
> > + compatible = "gpio-leds";
> > + led-0 {
> > + label = "bmc_heartbeat_amber";
> > + gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>;
> > + linux,default-trigger = "heartbeat";
> > + };
> > + };
> > +
> > + fio-leds {
> > + compatible = "gpio-leds";
> > + led-0 {
> > + label = "power_blue";
> > + gpios = <&fio_ioexp 4 GPIO_ACTIVE_HIGH>;
> > + };
> > + led-1 {
> > + label = "power_amber";
> > + gpios = <&fio_ioexp 5 GPIO_ACTIVE_LOW>;
> > + };
> > + led-2 {
> > + label = "id_blue";
> > + gpios = <&fio_ioexp 6 GPIO_ACTIVE_HIGH>;
> > + };
> > + led-3 {
> > + label = "id_amber";
> > + gpios = <&fio_ioexp 7 GPIO_ACTIVE_LOW>;
> > + };
> > + };
> > +};
> > +
> > +&fmc {
> > + status = "okay";
> > + flash at 0 {
> > + status = "okay";
> > + m25p,fast-read;
> > + label = "bmc";
> > + spi-max-frequency = <50000000>;
> > +#include "openbmc-flash-layout-128.dtsi"
> > + };
> > + flash at 1 {
> > + status = "okay";
> > + m25p,fast-read;
> > + label = "alt-bmc";
>
> Perhaps include the alt layout for 128M as well (which I recently
> applied).
>
This will be added in the next submission (v4).
> > + spi-max-frequency = <50000000>;
> > + };
> > +};
> > +
> > +&uart1 {
> > + status = "okay";
> > +};
> > +
> > +&uart3 {
> > + status = "okay";
> > +};
> > +
> > +&uart5 {
> > + status = "okay";
> > +};
> > +
> > +&uart_routing {
> > + status = "okay";
> > +};
> > +
> > +&mdio0 {
>
> The DTS coding style allows label references to be ordered
> alphabetically, which is my preference. Can you please fix this
> throughout?
>
Sorry, v3 has not applied with the DTS coding style.
I will update it in the next submission (v4).
> > + status = "okay";
> > + ethphy0: ethernet-phy at 0 {
> > + compatible = "ethernet-phy-ieee802.3-c22";
> > + reg = <0>;
> > + };
> > +};
> > +
> > +&mac0 {
> > + status = "okay";
> > + pinctrl-names = "default";
> > + phy-mode = "rgmii-rxid";
> > + max-speed = <1000>;
> > + phy-handle = <ðphy0>;
> > + pinctrl-0 = <&pinctrl_rgmii1_default>;
> > +};
> > +
> > +&ehci1 {
> > + status = "okay";
> > + hub at 1 {
> > + reg = <1>;
> > + hub at 2 {
> > + reg = <2>;
> > + hub at 1 {
> > + reg = <1>;
> > + device at 1 {
> > + reg = <1>;
> > + cp2112a: interface at 1 {
> > + reg = <1 1>;
> > +
> > + gpio-controller;
> > + interrupt-controller;
> > + #gpio-cells = <2>;
> > + #interrupt-cells = <2>;
> > +
> > + i2c20: i2c {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > + };
> > + };
> > + hub at 3 {
> > + reg = <3>;
> > + cp2112c: device at 2 {
> > + reg = <2>;
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
> > +
> > + gpio-line-names =
> > + "IOB0_MCP_P0_2-B",
> > + "IOB0_MCU_RST_L-O",
> > + "IOB0_MCU_RECOVERY_L-O",
> > + "IOB0_GLOBAL_WP-O",
> > + "IOB0_GLOBAL_ADDR_L_R-O",
> > + "IOB0_GLOBAL_ADDR_U_D-O",
> > + "IOB0_PWR_EN-O",
> > + "IOB0_MCU_READY_STATUS-I";
> > + };
> > + };
> > + hub at 4 {
> > + reg = <4>;
> > + cp2112d: device at 2 {
> > + reg = <2>;
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
> > +
> > + gpio-line-names =
> > + "IOB1_MCP_P0_2-B",
> > + "IOB1_MCU_RST_L-O",
> > + "IOB1_MCU_RECOVERY_L-O",
> > + "IOB1_GLOBAL_WP-O",
> > + "IOB1_GLOBAL_ADDR_L_R-O",
> > + "IOB1_GLOBAL_ADDR_U_D-O",
> > + "IOB1_PWR_EN-O",
> > + "IOB1_MCU_READY_STATUS-I";
> > + };
> > + };
> > + };
> > + hub at 2 {
> > + reg = <2>;
> > + device at 1 {
> > + reg = <1>;
> > + cp2112b: interface at 1 {
> > + reg = <1 1>;
> > +
> > + gpio-controller;
> > + interrupt-controller;
> > + #gpio-cells = <2>;
> > + #interrupt-cells = <2>;
> > +
> > + i2c21: i2c {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > + };
> > + };
> > + hub at 3 {
> > + reg = <3>;
> > + cp2112e: device at 2 {
> > + reg = <2>;
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
> > +
> > + gpio-line-names =
> > + "IOB2_MCP_P0_2-B",
> > + "IOB2_MCU_RST_L-O",
> > + "IOB2_MCU_RECOVERY_L-O",
> > + "IOB2_GLOBAL_WP-O",
> > + "IOB2_GLOBAL_ADDR_L_R-O",
> > + "IOB2_GLOBAL_ADDR_U_D-O",
> > + "IOB2_PWR_EN-O",
> > + "IOB2_MCU_READY_STATUS-I";
> > + };
> > + };
> > + hub at 4 {
> > + reg = <4>;
> > + cp2112f: device at 2 {
> > + reg = <2>;
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
> > +
> > + gpio-line-names =
> > + "IOB3_MCP_P0_2-B",
> > + "IOB3_MCU_RST_L-O",
> > + "IOB3_MCU_RECOVERY_L-O",
> > + "IOB3_GLOBAL_WP-O",
> > + "IOB3_GLOBAL_ADDR_L_R-O",
> > + "IOB3_GLOBAL_ADDR_U_D-O",
> > + "IOB3_PWR_EN-O",
> > + "IOB3_MCU_READY_STATUS-I";
> > + };
> > + };
> > + };
> > + };
> > + };
> > +};
> > +
> > +&adc0 {
> > + aspeed,int-vref-microvolt = <2500000>;
> > + status = "okay";
> > +
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default
> > + &pinctrl_adc2_default &pinctrl_adc3_default
> > + &pinctrl_adc4_default &pinctrl_adc5_default
> > + &pinctrl_adc6_default>;
> > +};
> > +
> > +&wdt1 {
> > + status = "okay";
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_wdtrst1_default>;
> > + aspeed,reset-type = "soc";
> > + aspeed,external-signal;
> > + aspeed,ext-push-pull;
> > + aspeed,ext-active-high;
> > + aspeed,ext-pulse-duration = <256>;
> > +};
> > +
> > +&i2c0 {
> > + status = "okay";
> > + aspeed,enable-byte;
> >
>
> ... Have you run `make dtbs_check`? A quick grep suggests this isn't a
> valid property.
>
I think v3 has fixed most of the failures in this DTS file.
The remaining failures originate from other included DTSI files.
> > +
> > + ssif-bmc at 10 {
> > + compatible = "ssif-bmc";
> > + reg = <0x10>;
> > + alert-gpios = <&gpio1 ASPEED_GPIO(D, 7) GPIO_ACTIVE_LOW>;
> > + timeout-ms = <5000>;
> > + };
> > +};
> > +
> > +&i2c1 {
> > + status = "okay";
> > +};
> > +
> > +&i2c2 {
> > + status = "okay";
> > +
> > + hpm0_ioexp_20: gpio at 20 {
> > + compatible = "nxp,pca9555";
>
> Is this a true nxp,pca9555, or a CPLD-based reimplementation? Same
> query for other instances...
>
There are physical IO expander chips on the module, not CPLD-based.
> Andrew
Potin
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