[PATCH RFC v2 0/3] pinctrl: aspeed: Add AST2700 SoC1 support

[Billy Tsai]

Legacy ASPEED pin controllers have historically not had a coherent
register interface. Control fields often had no consistent mapping to
individual pins, and configuring a function frequently required
coordinating multiple control bits across several registers. As a
result, the existing ASPEED pinctrl drivers rely on complex macro
infrastructure to describe the dependencies between pins, functions,
and register fields.

The pin controller for SoC1 in the AST2700 breaks from this legacy
design.

For SoC1, each pin maps directly to a dedicated function field in the
SCU register space that determines the active mux function for that
pin. This results in a much more regular register layout compared to
previous generations.

While the behaviour is conceptually similar to pinctrl-single, the
register layout and configuration model differ enough that reusing
pinctrl-single directly is not practical. Therefore this driver is
implemented as a SoC-specific pinctrl driver using static data tables
to describe the register layout.

The binding reuses the standard pinmux and generic pin configuration
schemas and does not introduce any custom Devicetree properties.

This series touches some of the same files as the AST2700 SoC0 pinctrl
series and may conflict if the two series are applied independently.

Known overlap includes:

  - Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
  - drivers/pinctrl/aspeed/Kconfig
  - drivers/pinctrl/aspeed/Makefile

The AST2700 SoC0 series can be found at:

https://lore.kernel.org/linux-aspeed/20260306-upstream_pinctrl-v4-0-ad4e8ab8b489@aspeedtech.com/

A binding example is not yet provided as there were differing opinions
during review about whether it should live in the SCU binding or the
pinctrl binding. I can add one in a follow-up revision once the
preferred location is agreed.

Signed-off-by: Billy Tsai <billy_tsai at aspeedtech.com>
---
Changes in v2:
- Updated the series title to focus on AST2700 SoC1 support.
- Reworked implementation to use static SoC-specific layout tables
  instead of a generic packed-field model.
- Dropped the generic "pinctrl-packed" driver approach.
- Removed custom Devicetree properties.
- Updated binding to reuse standard pinmux and generic pin
  configuration schemas.
- Link to v1: https://lore.kernel.org/r/20260213-pinctrl-single-bit-v1-0-c60f2fb80efb@aspeedtech.com

---
Billy Tsai (3):
      dt-bindings: mfd: aspeed,ast2x00-scu: Support AST2700 SoC1 pinctrl
      dt-bindings: pinctrl: Add aspeed,ast2700-soc1-pinctrl
      pinctrl: aspeed: Add AST2700 SoC1 support

 .../bindings/mfd/aspeed,ast2x00-scu.yaml           |    1 +
 .../pinctrl/aspeed,ast2700-soc1-pinctrl.yaml       |  449 ++++++
 drivers/pinctrl/aspeed/Kconfig                     |   13 +
 drivers/pinctrl/aspeed/Makefile                    |    1 +
 drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c    | 1573 ++++++++++++++++++++
 5 files changed, 2037 insertions(+)
---
base-commit: af4e9ef3d78420feb8fe58cd9a1ab80c501b3c08
change-id: 20260211-pinctrl-single-bit-da213f282c95

Best regards,
-- 
Billy Tsai <billy_tsai at aspeedtech.com>