[PATCH 0/5] Add Aspeed G7 sgpio support

[Linus Walleij]

On Sat, Jan 17, 2026 at 12:17 PM Billy Tsai <billy_tsai at aspeedtech.com> wrote:

> The Aspeed 7th generation SoC features two SGPIO master controllers: both
> with 256 serial inputs and outputs. The main difference from the previous
> generation is that the control logic has been updated to support
> per-pin control, allowing each pin to have its own 32-bit register for
> configuring value, interrupt type, and more.
> This patch serial also add low-level operations (llops) to abstract the
> register access for SGPIO registers making it easier to extend the driver
> to support different hardware register layouts.
>
> Signed-off-by: Billy Tsai <billy_tsai at aspeedtech.com>

Changes look reasonable to me!
Reviewed-by: Linus Walleij <linusw at kernel.org>

Yours,
Linus Walleij