No subject
Tue Sep 9 18:45:02 AEST 2025
Using interrupts-extended we can represent the route configuration with
a phandle to the upstream controller on the cascaded node. To avoid
some arbitrary interrupt index choices at the node for INTC0, I think
it's worth describing the register sets for interrupt sets Ma, Md and
Me as subnodes of INTC0 with their own interrupt resources. This feels
reasonably tidy, as the selection of the Ma, Md or Me sets completely
determines its ultimate index at the PSP GIC. Doing so also removes
them from needing to be described if any changes to some default route
configuration are required by the platform, necessitating overriding
the interrupts-extended property of the INTC0 node.
The only curiosity of this approach is that the interrupt-controller
nodes for the non-PSP processors need to be described so we can
reference them via phandles for the purpose of routing the interrupts.
As these controllers are not mapped in the physical address space of
the PSP we need the devicetree to inform the kernel as much.
Here's an example pseudo-devicetree. Of course there are elements that
need more work, but I feel we can mine it for parts.
Cheers,
Andrew
/ {
primary {
compatible =3D "simple-bus";
#address-cells =3D <1>;
#size-cells =3D <1>;
ranges;
intc0: interrupt-controller at 12100000 {
compatible =3D "aspeed,ast2700-intc0-a1";
reg =3D <0x12100000 0x1b00>;
#address-cells =3D <1>;
#size-cells =3D <1>;
ranges;
interrupt-controller;
#interrupt-cells =3D <2>;
interrupts-extended =3D
#if GIC
/* GICINT0 */ <&gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
#elif SSP
/* SSPINT0 */ <&ssp_nvic 0 0>,
#else /* TSP */
/* TSPINT0 */ <&tsp_nvic 0 0>,
#endif
/* ... */
#if GIC_128 /* Route merged 128-159 interrupts to GICINT128 */
/* 128 */ <&gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
#elif GIC_160 /* Route merged 128-159 interrupts to GICINT160 */
/* 128 */ <&gic GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
#elif GIC_176 /* Route merged 128-159 interrupts to GICINT176 */
/* 128 */ <&gic GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
#elif SSP
/* 128 */ <&ssp_nvic 128 0>,
#else /* TSP */
/* 128 */ <&tsp_nvic 128 0>,
#endif
/* ... */
/* 186 */ <&gic 186 0>;
intcm0: interrupt-controller at 12101b00 {
compatible =3D "aspeed,ast2700-intcm-a1";
reg =3D <0x12101b00 0x10>;
interrupt-controller;
#interrupt-cells =3D <2>;
interrupt-parent =3D <&gic>;
interrupts =3D
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
};
intcm30: interrupt-controller at 12101b10 {
compatible =3D "aspeed,ast2700-intcm-a1";
reg =3D <0x12101b10 0x10>;
interrupt-controller;
#interrupt-cells =3D <2>;
interrupt-parent =3D <&gic>;
interrupts =3D
<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
};
intcm40: interrupt-controller at 12101b20 {
compatible =3D "aspeed,ast2700-intcm-a1";
reg =3D <0x12101b20 0x10>;
interrupt-controller;
#interrupt-cells =3D <2>;
interrupt-parent =3D <&gic>;
interrupts =3D
<GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
};
};
intc1: interrupt-controller at 14c18000 {
compatible =3D "aspeed,ast2700-intc1-a1";
reg =3D <0x14c18000 0x1000>;
interrupt-controller;
#interrupt-cells =3D <2>;
interrupts-extended =3D
#if M0
/* 0 */ <&intcm0 0 IRQ_TYPE_LEVEL_HIGH>,
#elif C0
/* 0 */ <&intc0 128 IRQ_TYPE_LEVEL_HIGH>,
#elif M10
/* 0 */ <&ssp_nvic 160 0>,
#elif M20
/* 0 */ <&tsp_nvic 160 0>,
#elif M30
/* 0 */ <&intcm30 0 IRQ_TYPE_LEVEL_HIGH>,
#elif M40
/* 0 */ <&intcm40 0 IRQ_TYPE_LEVEL_HIGH>,
#else /* B */
/* 0 */ <&aplic 128 IRQ_TYPE_LEVEL_HIGH>,
#endif
/* ... */
};
vuart1: serial at 1e787000 {
compatible =3D "aspeed,ast2700-vuart";
reg =3D <0x14c30000 0x1000>;
reg-shift =3D <2>;
interrupts-extended =3D <&intc1 17 IRQ_TYPE_LEVEL_HIGH>;
};
gic: interrupt-controller at fff01000 {
compatible =3D "arm,gic-400";
#interrupt-cells =3D <3>;
#address-cells =3D <0>;
interrupt-controller;
reg =3D <0x0 0xfff01000 0 0x1000>,
<0x0 0xfff02000 0 0x2000>,
<0x0 0xfff04000 0 0x2000>,
<0x0 0xfff06000 0 0x2000>;
interrupts =3D <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HI=
GH)>;
};
};
secondary {
#address-cells =3D <2>;
/* https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/t=
ree/drivers/of/address.c?h=3Dv6.16#n491 */
#size-cells =3D <0>;
/* https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/t=
ree/drivers/of/address.c?h=3Dv6.16#n430 */
ssp_nvic: interrupt-controller at 1,e000e100 {
compatible =3D "arm,v7m-nvic";
#interrupt-cells =3D <2>;
#address-cells =3D <0>;
interrupt-controller;
reg =3D <1 0xe000e100>;
};
};
tertiary {
#address-cells =3D <2>;
#size-cells =3D <0>;
tsp_nvic: interrupt-controller at 2,e000e100 {
compatible =3D "arm,v7m-nvic";
#interrupt-cells =3D <2>;
#address-cells =3D <0>;
interrupt-controller;
reg =3D <2 0xe000e100>;
};
};
bootmcu {
#address-cells =3D <2>;
#size-cells =3D <0>;
aplic1: interrupt-controller at 3,d000000 {
compatible =3D "riscv,aplic";
interrupts-extended =3D <&cpu1_intc 9>,
reg =3D <3 0xd000000>;
interrupt-controller;
#interrupt-cells =3D <2>;
riscv,num-sources =3D <480>;
};
};
};
More information about the Linux-aspeed
mailing list