[PATCH v1] ARM: dts: aspeed: yosemite4: Revise quad mode to dual mode

[Andrew Jeffery]

On Tue, 2024-09-10 at 13:13 +0800, Delphine CC Chiu wrote:
> From: Ricky CX Wu <ricky.cx.wu.wiwynn at gmail.com>
> 
> Revise quad mode to dual mode to avoid WP pin influnece the SPI.
> 
> Signed-off-by: Ricky CX Wu <ricky.cx.wu.wiwynn at gmail.com>
> Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu at wiwynn.com>
> ---
>  .../arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts | 8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
> index 98477792aa00..3073ade6d77c 100644
> --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
> +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
> @@ -105,15 +105,17 @@ flash at 0 {
>  		status = "okay";
>  		m25p,fast-read;
>  		label = "bmc";
> -		spi-rx-bus-width = <4>;
> +		spi-tx-bus-width = <2>;
> +		spi-rx-bus-width = <2>;
>  		spi-max-frequency = <50000000>;
> -#include "openbmc-flash-layout-64.dtsi"
> +#include "openbmc-flash-layout-128.dtsi"

This is a bit more drastic than changing the bus mode.

Can you please split that out to a separate change with some
justification in the commit message? For instance, was the chip changed
too? Or were you using the 64M layout or a 128M chip the whole time?

Andrew