[PATCH v2 8/9] arm64: dts: aspeed: Add initial AST27XX device tree

[Krzysztof Kozlowski]

On 02/08/2024 11:05, Kevin Chen wrote:
> Add aspeed-g7.dtsi to be AST27XX device tree.

Hardware description is missing, e.g. answering why you have two "soc"
nodes.
> 
> Signed-off-by: Kevin Chen <kevin_chen at aspeedtech.com>



> +	soc0: soc at 10000000 {
> +		compatible = "simple-bus";
> +		reg = <0x0 0x10000000 0x0 0x10000000>;
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		gic: interrupt-controller at 12200000 {
> +			compatible = "arm,gic-v3";
> +			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> +			#interrupt-cells = <3>;
> +			interrupt-controller;
> +			interrupt-parent = <&gic>;
> +			reg = <0 0x12200000 0 0x10000>, /* GICD */
> +				  <0 0x12280000 0 0x80000>, /* GICR */
> +				  <0 0x40440000 0 0x1000>;  /* GICC */

Still the same things to fix... Please go to the DTS coding style and
read what is the order of properties.

<form letter>
This is a friendly reminder during the review process.

It seems my or other reviewer's previous comments were not fully
addressed. Maybe the feedback got lost between the quotes, maybe you
just forgot to apply it. Please go back to the previous discussion and
either implement all requested changes or keep discussing them.

Thank you.
</form letter>


> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +		};


Best regards,
Krzysztof