[PATCH 0/4] Remove LPC register partitioning
chiawei_wang at aspeedtech.com
Wed Sep 30 17:54:30 AEST 2020
> -----Original Message-----
> From: Andrew Jeffery <andrew at aj.id.au>
> Sent: Wednesday, September 30, 2020 2:12 PM
> To: Ryan Chen <ryan_chen at aspeedtech.com>; ChiaWei Wang
> <chiawei_wang at aspeedtech.com>; Joel Stanley <joel at jms.id.au>
> Subject: Re: [PATCH 0/4] Remove LPC register partitioning
> On Mon, 28 Sep 2020, at 17:13, Ryan Chen wrote:
> > Hello Joel & Andrew,
> > Those patches are more organize for ASPEED SOC LPC register layout.
> > Does those patches have any feedback?
> I support getting the problem fixed. However, the series also needs to fix the
> LPC devicetree binding at
> What's proposed isn't backwards compatible. We need to agree that a
> breaking change is the way we want to go and get Rob's buy-in. Given the
> impact of the change I'd prefer we don't try to maintain backwards
> compatibility. All known users of the binding ship the dtb with the kernel.
> Can we get a v2 with the binding documentation fixed? That will probably need
> some review.
Yes, I will fix the binding documentation and resend the v2 patch for the review.
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