[PATCH 2/2] mmc: sdhci-of-aspeed: Fix clock divider calculation
joel at jms.id.au
Fri Jul 10 13:04:03 AEST 2020
On Fri, 10 Jul 2020 at 01:14, Andrew Jeffery <andrew at aj.id.au> wrote:
> On Fri, 10 Jul 2020, at 05:27, Eddie James wrote:
> > When calculating the clock divider, start dividing at 2 instead of 1.
> > The divider is divided by two at the end of the calculation, so starting
> > at 1 may result in a divider of 0, which shouldn't happen.
> > Signed-off-by: Eddie James <eajames at linux.ibm.com>
> Reviewed-by: Andrew Jeffery <andrew at aj.id.au>
Acked-by: Joel Stanley <joel at jms.id.au>
Fixes: d3d04f6c330a ("clk: Add support for AST2600 SoC")
Stephen, I think this should go to stable too along with 1/2.
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