[PATCH 2/2] media: aspeed: fix clock handling logic

[Jae Hyun Yoo]

Hi Stephen,

On 12/17/2020 2:46 AM, Stephen Boyd wrote:
> Quoting Jae Hyun Yoo (2020-12-08 09:16:29)
>> Hi Joel,
>>
>> On 12/7/2020 6:39 PM, Joel Stanley wrote:
>>> On Mon, 7 Dec 2020 at 16:33, Jae Hyun Yoo <jae.hyun.yoo at linux.intel.com> wrote:
>>>>
>>>> Video engine uses eclk and vclk for its clock sources and its reset
>>>> control is coupled with eclk so the current clock enabling sequence works
>>>> like below.
>>>>
>>>>    Enable eclk
>>>>    De-assert Video Engine reset
>>>>    10ms delay
>>>>    Enable vclk
>>>
>>> This is the case after " clk: ast2600: fix reset settings for eclk and
>>> vclk" is applied, correct? Without that patch applied the reset
>>> sequence is correct by accident for the 2600, but it will be wrong for
>>> the 2500?
>>
>> Correct. Video Engine reset was coupled with eclk for AST2500 and vclk
>> for AST2600 so above sequence was observed only in AST2500. As you said,
>> AST2600 didn't make the issue by accident but the clk/reset pair should
>> be fixed by this patch series.
> 
> So should the two patches be squashed together and go through the
> media tree?
> 

The first patch should go through clk tree, and the second one (this
patch) should go through media tree. Both patches should be applied at
the same time. Should I squash them in this case?