[PATCH v2 2/2] clk: aspeed: Add RMII RCLK gates for both AST2500 MACs

Joel Stanley joel at jms.id.au
Fri Oct 11 10:41:35 AEDT 2019

On Thu, 10 Oct 2019 at 02:06, Andrew Jeffery <andrew at aj.id.au> wrote:
> RCLK is a fixed 50MHz clock derived from HPLL that is described by a
> single gate for each MAC.
> Signed-off-by: Andrew Jeffery <andrew at aj.id.au>

Reviewed-by: Joel Stanley <joel at jms.id.au>

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