[PATCH 1/2] i2c: aspeed: allow to customize base clock divisor

Ryan Chen ryan_chen at aspeedtech.com
Thu Jun 20 18:01:58 AEST 2019

Hello Tao,
	Let me more clear. When you set (3, 15, 14) the device sometimes response nack. 
	but when you set (4, 7, 7), the device always ack. Am I right? 

-----Original Message-----
From: Tao Ren [mailto:taoren at fb.com] 
Sent: Thursday, June 20, 2019 3:57 PM
To: Ryan Chen <ryan_chen at aspeedtech.com>; Brendan Higgins <brendanhiggins at google.com>
Cc: Mark Rutland <mark.rutland at arm.com>; devicetree <devicetree at vger.kernel.org>; linux-aspeed at lists.ozlabs.org; OpenBMC Maillist <openbmc at lists.ozlabs.org>; Linux Kernel Mailing List <linux-kernel at vger.kernel.org>; Rob Herring <robh+dt at kernel.org>; Linux ARM <linux-arm-kernel at lists.infradead.org>; linux-i2c at vger.kernel.org
Subject: Re: [PATCH 1/2] i2c: aspeed: allow to customize base clock divisor

On 6/20/19 12:29 AM, Ryan Chen wrote:
> Hello Tao,
> 	Our recommend about clk divider setting is follow the datasheet clock setting table for clock divisor. 
> Ryan  

Thanks Ryan for the response. Could you also share some recommendations/hints on how to solve the intermittent i2c transaction failures on Facebook AST2500 BMC platforms?

BTW, the patch is not aimed at modifying the existing formula of calculating clock settings in i2c-aspeed driver: people still get the recommended settings by default. The goal of the patch is to allow people to customize clock settings in case the default/recommended one doesn't work.



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