[PATCH v2 02/12] irqchip: Add Aspeed SCU interrupt controller

Andrew Jeffery andrew at aj.id.au
Wed Dec 11 11:32:08 AEDT 2019

On Fri, 6 Dec 2019, at 03:45, Eddie James wrote:
> The Aspeed SOCs provide some interrupts through the System Control
> Unit registers. Add an interrupt controller that provides these
> interrupts to the system.
> Signed-off-by: Eddie James <eajames at linux.ibm.com>

Reviewed-by: Andrew Jeffery <andrew at aj.id.au>

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