[PATCH] clk: aspeed: Add SDIO gate

[Stephen Boyd]

Quoting Andrew Jeffery (2019-07-10 07:10:09)
> From: Joel Stanley <joel at jms.id.au>
> 
> The clock divisor comes with an enable bit (gate). This was not
> implemented as we didn't have access to SD hardware when writing the
> driver. Now that we can test it, add the gate as a parent to the
> divisor.
> 
> There is no reason to expose the gate separately, so users will enable
> it by turning on the ASPEED_CLK_SDIO divisor.
> 
> Signed-off-by: Joel Stanley <joel at jms.id.au>
> [aj: Minor style cleanup]
> Signed-off-by: Andrew Jeffery <andrew at aj.id.au>
> ---

Applied to clk-next