[PATCH v10 0/4] Add uacce module for Accelerator
Jonathan.Cameron at Huawei.com
Fri Jan 10 21:08:18 AEDT 2020
On Fri, 10 Jan 2020 15:03:25 +0800
zhangfei <zhangfei.gao at linaro.org> wrote:
> On 2020/1/10 上午1:49, Jonathan Cameron wrote:
> > On Mon, 16 Dec 2019 11:08:13 +0800
> > Zhangfei Gao <zhangfei.gao at linaro.org> wrote:
> >> Uacce (Unified/User-space-access-intended Accelerator Framework) targets to
> >> provide Shared Virtual Addressing (SVA) between accelerators and processes.
> >> So accelerator can access any data structure of the main cpu.
> >> This differs from the data sharing between cpu and io device, which share
> >> data content rather than address.
> >> Because of unified address, hardware and user space of process can share
> >> the same virtual address in the communication.
> >> Uacce is intended to be used with Jean Philippe Brucker's SVA
> >> patchset, which enables IO side page fault and PASID support.
> >> We have keep verifying with Jean's sva patchset 
> >> We also keep verifying with Eric's SMMUv3 Nested Stage patches 
> > Hi Zhangfei Gao,
> > Just to check my understanding...
> > This patch set is not dependent on either 2 or 3?
> > To use it on our hardware, we need 2, but the interfaces used are already
> > upstream, so this could move forwards in parallel.
> patch 1, 2 is for uacce.
> patch 3, 4 is an example using uacce, which happen to be crypto.
Sorry, I wasn't clear enough.
Question is whether we need Jean's sva patch set  to merge this?
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