[PATCH v6 2/3] uacce: add uacce driver
jglisse at redhat.com
Fri Oct 25 01:17:59 AEDT 2019
On Thu, Oct 24, 2019 at 02:41:29PM +0800, Kenneth Lee wrote:
> On Tue, Oct 22, 2019 at 02:49:29PM -0400, Jerome Glisse wrote:
> > Date: Tue, 22 Oct 2019 14:49:29 -0400
> > From: Jerome Glisse <jglisse at redhat.com>
> > To: Zhangfei Gao <zhangfei.gao at linaro.org>
> > Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>, Arnd Bergmann
> > <arnd at arndb.de>, Herbert Xu <herbert at gondor.apana.org.au>,
> > jonathan.cameron at huawei.com, grant.likely at arm.com, jean-philippe
> > <jean-philippe at linaro.org>, ilias.apalodimas at linaro.org,
> > francois.ozog at linaro.org, kenneth-lee-2012 at foxmail.com, Wangzhou
> > <wangzhou1 at hisilicon.com>, "haojian . zhuang" <haojian.zhuang at linaro.org>,
> > Zaibo Xu <xuzaibo at huawei.com>, linux-kernel at vger.kernel.org,
> > linux-crypto at vger.kernel.org, Kenneth Lee <liguozhu at hisilicon.com>,
> > linux-accelerators at lists.ozlabs.org
> > Subject: Re: [PATCH v6 2/3] uacce: add uacce driver
> > Message-ID: <20191022184929.GC5169 at redhat.com>
> > On Wed, Oct 16, 2019 at 04:34:32PM +0800, Zhangfei Gao wrote:
> > > From: Kenneth Lee <liguozhu at hisilicon.com>
> > >
> > > Uacce (Unified/User-space-access-intended Accelerator Framework) targets to
> > > provide Shared Virtual Addressing (SVA) between accelerators and processes.
> > > So accelerator can access any data structure of the main cpu.
> > > This differs from the data sharing between cpu and io device, which share
> > > data content rather than address.
> > > Since unified address, hardware and user space of process can share the
> > > same virtual address in the communication.
> > >
> > > Uacce create a chrdev for every registration, the queue is allocated to
> > > the process when the chrdev is opened. Then the process can access the
> > > hardware resource by interact with the queue file. By mmap the queue
> > > file space to user space, the process can directly put requests to the
> > > hardware without syscall to the kernel space.
> > You need to remove all API that is not use by your first driver as
> > it will most likely bit rot without users. It is way better to add
> > things when a driver start to make use of it.
> Yes. Good point. Thank you:)
> > I am still not convince of the value of adding a new framework here
> > with only a single device as an example. It looks similar to some of
> > the fpga devices. Saddly because framework layering is not something
> > that exist i guess inventing a new framework is the only answer when
> > you can not quite fit into an existing one.
> > More fundamental question is why do you need to change the IOMMU
> > domain of the device ? I do not see any reason for that unless the
> > PASID has some restriction on ARM that i do not know of.
> But I think this is the only way. As my understanding, by default, the
> system creates a DMA IOMMU domain for each device behine an IOMMU. If
> you want to call iommu interface directly, we have to rebind the device
> to an unmanaged domain.
Why would you need to call iommu directly ? On some GPUs we do use
PASID and we do not rebind to different domain, we just don't mess
with that. So i do not see any reason to change the domain.
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