[PATCH v2 06/10] mmc: omap_hsmmc: add support for pbias configuration in dt

[Balaji T K]

On Thursday 13 June 2013 03:32 PM, Laurent Pinchart wrote:
> On Thursday 13 June 2013 02:53:54 Tony Lindgren wrote:
>> * Linus Walleij <linus.walleij at linaro.org> [130613 02:42]:
>>> On Thu, Jun 6, 2013 at 9:14 PM, Balaji T K <balajitk at ti.com> wrote:
>>>> PBIAS register configuration is based on the regulator voltage
>>>> which supplies these pbias cells, sd i/o pads.
>>>> With PBIAS register address and bit definitions different across
>>>> omap[3,4,5], Simplify PBIAS configuration under three different
>>>> regulator voltage levels - O V, 1.8 V, 3 V. Corresponding pinctrl states
>>>> are defined as pbias_off, pbias_1v8, pbias_3v.
>>>>
>>>> pinctrl state mmc_init is used for configuring speed mode, loopback
>>>> clock (in devconf0/devconf1/prog_io1 register for omap3) and pull
>>>> strength configuration (in control_mmc1 for omap4)
>>>>
>>>> Signed-off-by: Balaji T K <balajitk at ti.com>
>>>
>>> You *need* Lee Jones and Mark Brown to review this.
>>> Maybe Laurent has something to add too.
>>>
>>> Ux500 had the very same thing, and there this was solved using
>>> a GPIO regulator for "vqmmc" a level-shifter. I vaguely remember
>>> Laurent doing something similar with the SH stuff.
>
> The SH pinctrl driver registers an MMC regulator. The code is available at
> git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git. Look at
> drivers/pinctrl/sh-pfc/pfc-sh73a0.c in tags/renesas-next-20130611v2.
>

Hi,

Thanks for the link, I think I need some time to understand
where pfc->window[1].virt is coming from.