[PATCH v5 09/10] clk: tegra: Implement clocks for Tegra114

[Peter De Schrijver]

> 
> > > +       /* xusb_hs_src */
> > > +       val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC);
> > > +       val |= BIT(25); /* always select PLLU_60M */
> > > +       writel(val, clk_base + CLK_SOURCE_XUSB_SS_SRC);
> > > +
> > > +       clk = clk_register_fixed_factor(NULL, "xusb_hs_src", "pll_u_60M", 0,
> > > +                                       1, 1);
> > > +       clks[xusb_hs_src] = clk;
> > > +
> > 
> > With device tree we can directly use pll_u_60M, no need to register 
> > clock with fixed factor 1.
> 
> This is true for now. In the future these clocks will need to be dvfs aware
> though. I think it makes sense to have a separate clock then?
> 

As this seems to be a different clock (ie. the hw allows you to select a
different parent), I think keeping this node makes sense.

Cheers,

Peter.