[PATCH 10/20] x86: fdt: Create basic .dtsi file for coreboot

[Simon Glass]

This contains just the minimum information for a coreboot-based board.

Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
Signed-off-by: Gabe Black <gabeblack at chromium.org>
Signed-off-by: Simon Glass <sjg at chromium.org>
---
 arch/x86/dts/coreboot.dtsi |   16 ++++++++++++++++
 arch/x86/dts/skeleton.dtsi |   13 +++++++++++++
 2 files changed, 29 insertions(+), 0 deletions(-)
 create mode 100644 arch/x86/dts/coreboot.dtsi
 create mode 100644 arch/x86/dts/skeleton.dtsi

diff --git a/arch/x86/dts/coreboot.dtsi b/arch/x86/dts/coreboot.dtsi
new file mode 100644
index 0000000..4862a59
--- /dev/null
+++ b/arch/x86/dts/coreboot.dtsi
@@ -0,0 +1,16 @@
+/include/ "skeleton.dtsi"
+
+/ {
+	aliases {
+		console = "/serial";
+	};
+
+	serial {
+		compatible = "ns16550";
+		reg-shift = <1>;
+		io-mapped = <1>;
+		multiplier = <1>;
+		baudrate = <115200>;
+		status = "disabled";
+	};
+};
diff --git a/arch/x86/dts/skeleton.dtsi b/arch/x86/dts/skeleton.dtsi
new file mode 100644
index 0000000..b41d241
--- /dev/null
+++ b/arch/x86/dts/skeleton.dtsi
@@ -0,0 +1,13 @@
+/*
+ * Skeleton device tree; the bare minimum needed to boot; just include and
+ * add a compatible value.  The bootloader will typically populate the memory
+ * node.
+ */
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	chosen { };
+	aliases { };
+	memory { device_type = "memory"; reg = <0 0>; };
+};
-- 
1.7.7.3