[PATCH v2 4/7] tegra: fdt: Add NAND controller binding and definitions

[Scott Wood]

On 04/17/2012 01:44 PM, Simon Glass wrote:
> Hi,
> 
> On Tue, Apr 17, 2012 at 11:38 AM, Scott Wood <scottwood at freescale.com> wrote:
>> On 04/17/2012 01:33 PM, Simon Glass wrote:
>>> Hi Stephen,
>>>
>>> On Fri, Apr 13, 2012 at 2:05 PM, Stephen Warren <swarren at wwwdotorg.org> wrote:
>>>> On 04/13/2012 12:29 PM, Simon Glass wrote:
>>>>> +nand-controller at 0x70008000 {
>>>>> +     compatible = "nvidia,tegra20-nand";
>>>>> +     wp-gpios = <&gpio 59 0>;                /* PH3 */
>>>>> +     nvidia,width = <8>;
>>>>> +     nvidia,timing = <26 100 20 80 20 10 12 10 70>;
>>>>> +     nand at 0 {
>>>>> +             compatible = "hynix,hy27uf4g2b", "nand-flash";
>>>>
>>>> The TRM says there can be up to 8 chip selects. Don't the NAND device
>>>> sub-nodes need a reg property to indicate which chip-select they're on?
>>>
>>> We don't have driver support for this at present.
>>
>> That shouldn't matter.  The device tree is about describing the
>> hardware.  Ideally the device tree shouldn't have to change if in the
>> future you do get driver support for it.
>>
>> Also, unit addresses should only be present if reg is present, and they
>> should match.
> 
> OK I will leave @0 in there, and add a reg property to the node.

Also set #address-cells = <1> and #size-cells = <0> in the controller node.

-Scott