[PATCH V3 2/5] arm/dt: add very basic dts file for babbage board
Jason Liu
jason.hui at linaro.org
Wed Mar 9 16:19:30 EST 2011
Signed-off-by: Jason Liu <r64343 at freescale.com>
Singed-off-by: Rob Herring <robherring2 at gmail.com>
---
arch/arm/boot/dts/babbage.dts | 110 +++++++++++++++++++++++++++++++++++++++++
1 files changed, 110 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/babbage.dts b/arch/arm/boot/dts/babbage.dts
new file mode 100644
index 0000000..303dcd5
--- /dev/null
+++ b/arch/arm/boot/dts/babbage.dts
@@ -0,0 +1,110 @@
+/dts-v1/;
+
+/ {
+ model = "Freescale i.MX51 Babbage";
+ compatible = "fsl,mx51-babbage";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&tzic>;
+
+ memory {
+ reg = <0x90000000 0x20000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttymxc0,115200n8 debug earlyprintk ip=dhcp";
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges;
+
+ tzic: tz-interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ reg = <0xe0000000 0x1000>;
+ compatible = "fsl,imx51-tzic";
+ };
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ uart0_clk: uart0 {
+ compatible = "clock";
+ clock-outputs = "imx-uart.0";
+ };
+
+ uart1_clk: uart1 {
+ compatible = "clock";
+ clock-outputs = "imx-uart.1";
+ };
+
+ uart2_clk: uart2 {
+ compatible = "clock";
+ clock-outputs = "imx-uart.2";
+ };
+
+ fec_clk: fec {
+ compatible = "clock";
+ clock-outputs = "fec.0";
+ };
+ };
+
+ aips at 73f00000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0x73f00000 0x100000>;
+
+ imx-uart at bc000 {
+ compatible = "fsl,imx51-uart";
+ reg = <0xbc000 0x1000>;
+ interrupts = <0x1f>;
+ fsl,has-rts-cts;
+ uart-clock = <&uart0_clk>, "uart";
+ };
+
+ imx-uart at c0000 {
+ compatible = "fsl,imx51-uart";
+ reg = <0xc0000 0x1000>;
+ interrupts = <0x20>;
+ fsl,has-rts-cts;
+ uart-clock = <&uart1_clk>, "uart";
+ };
+ };
+
+ spba at 70000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0x70000000 0x100000>;
+
+ imx-uart at c000 {
+ compatible = "fsl,imx51-uart";
+ reg = <0xc000 0x1000>;
+ interrupts = <0x21>;
+ fsl,has-rts-cts;
+ uart-clock = <&uart2_clk>, "uart";
+ };
+ };
+
+ aips at 83f00000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0x83f00000 0x100000>;
+
+ fec at ec000 {
+ compatible = "fsl,imx-fec";
+ reg = <0xec000 0x1000>;
+ interrupts = <0x57>;
+ fec_clk-clock = <&fec_clk>, "fec";
+ };
+ };
+};
--
1.7.1
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