[PATCH 1/5] arm/dts: babbage: add gpt and uart related clock nodes
Shawn Guo
shawn.guo at freescale.com
Tue Mar 8 18:07:17 EST 2011
On Tue, Mar 08, 2011 at 02:56:52PM +0800, Jason Hui wrote:
> Hi, Shawn,
>
> On Tue, Mar 8, 2011 at 12:22 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
> > The patch is to add all gpt, uart related dt clock nodes for babbage.
> > It sticks to the clock name used in clock-mx51-mx53.c, so that
> > everything gets consistent to Reference Manual. For example, the
> > numbering in clock name usually starts from 1, while 'reg' property
> > numbering starts from 0 to easy clock binding.
> >
> > Besides the generally used clock bindings, the following properties
> > are proposed in this patch.
> >
> > * clock-alias
> > Like clock-outputs to reflect cl->dev_id, property clock-alias is
> > defined to reflect cl->con_id.
> >
> > * clock-depend
> > The mxc 'struct clk' has the member 'secondary' to refer to the clock
> > that the 'clk' has dependency on. This 'secondary' clock needs to be
> > on whenever the 'clk' is set to on. This clock-depend property is
> > defined to reflect this 'secondary' clock.
> >
> > Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
> > ---
> > arch/arm/boot/dts/babbage.dts | 162 +++++++++++++++++++++++++++++++++++++++--
> > 1 files changed, 156 insertions(+), 6 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/babbage.dts b/arch/arm/boot/dts/babbage.dts
> > index 46a3071..1774cec 100644
> > --- a/arch/arm/boot/dts/babbage.dts
> > +++ b/arch/arm/boot/dts/babbage.dts
> > @@ -35,19 +35,169 @@
> > #address-cells = <1>;
> > #size-cells = <0>;
> >
> > - uart0_clk: uart at 0 {
> > + ckil_clk: clkil {
> > + compatible = "fixed-clock";
> > + #frequency-cells = <1>;
> > + clock-outputs = "clil";
> > + clock-frequency = <32768>;
> > + };
> > +
> > + ckih_clk: ckih {
> > + compatible = "fixed-clock";
> > + #frequency-cells = <1>;
> > + clock-outputs = "ckih";
> > + clock-frequency = <22579200>;
> > + };
> > +
> > + osc_clk: soc {
> > + compatible = "fixed-clock";
> > + #frequency-cells = <1>;
> > + clock-outputs = "osc";
> > + clock-frequency = <24000000>;
> > + };
> > +
> > + pll1_main_clk: pll1_main {
> > + compatible = "clock";
> > + reg = <0>;
> > + clock-outputs = "pll1_main";
> > + clock-source = <&osc_clk>;
> > + };
> > +
> > + pll1_sw_clk: pll_switch at 0 {
> > + compatible = "clock";
> > + reg = <0>;
> > + clock-outputs = "pll1_sw";
> > + clock-source = <&pll1_main_clk>;
> > + };
> > +
> > + pll2_sw_clk: pll_switch at 1 {
> > + compatible = "clock";
> > + reg = <1>;
> > + clock-outputs = "pll2_sw";
> > + clock-source = <&osc_clk>;
> > + };
> >
>
> It seems that you mis-used the reg property, it need fixed globally.
>
I guessed it out from Grant's comment on your babbage.dts as below.
--- quote begin ---
>> + uart_clk0: uart at 0 {
@0 should only be specified if the node has a 'reg = <0>' property.
In this case it doesn't so either 'reg' should be added, or '@0'
should be removed.
--- quote end ---
--
Regards,
Shawn
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