[PATCH] of/fdt: Add unflatten_partial_device_tree

Grant Likely grant.likely at secretlab.ca
Wed Jul 7 08:57:13 EST 2010


On Thu, Jul 1, 2010 at 10:18 PM, David Gibson
<david at gibson.dropbear.id.au> wrote:
> On Thu, Jul 01, 2010 at 08:59:16AM -0700, Stephen Neuendorffer wrote:
> [snip]
>> Going down this path, I've taken an approach where the PCI driver reads
>> the PCI BARs which are set earlier
>> and stuffs the correct ranges=<> property into the device tree.  I think
>> this is necessary because (I believe)
>> powerpc programs the BARs based on the flat device tree, whereas on X86,
>> the BIOS enumerates the BARs and
>
> Only on some powerpc subplatforms, I believe.  Some platforms have
> minimal firmwares that either don't configure the BARs at all, or get
> them so hopelessly wrong that we have to reconfigure everything anyway.

On powerpc without OFW, typically the device tree specifies the host
bridge BARs, and then the kernel enumerates the devices.  The device
tree usually doesn't specify where the child devices get located, but
it does tell the PCI subsystem what address ranges are available.

If OFW is present, then the kernel can usually adopt whatever OFW did
during enumeration.

In your situation, yes you will have to read the BAR settings provided
by the PCI subsystem and populate the ranges property correctly.

>> OF: ** translation for device /plb at 0/xps-hwicap at 80030000 **
>> OF: bus is default (na=1, ns=1) on /plb at 0
>> OF: translating address: 80030000
>> OF: parent bus is default (na=1, ns=1) on /
>> OF: walking ranges...
>> OF: default map, cp=80000000, s=10000000, da=80030000
>> OF: parent translation for: d0000000
>> OF: with offset: 30000
>> OF: one level translation: d0030000
>> OF: reached root node
>> of_icap d0030000.xps-hwicap: Xilinx icap port driver
>> of_icap d0030000.xps-hwicap: Couldn't lock memory region at d0030000
>> of_icap: probe of d0030000.xps-hwicap failed with error -16
>>
>> Apparently because the address region is already assigned to the PCI
>> device.  I think I need to figure out how
>> PCI bridges declare their address range but don't lock it, so that the
>> device in the FPGA (in this case the ICAP) can
>> claim it later.

You also need to make sure your devices are children of the pci_device
so that they can claim the memory regions that they use.  If it isn't
a child, then it cannot claim the same region.

g.

-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.


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