PCI bus node location

[Grant Likely]

On Tue, Nov 10, 2009 at 9:55 AM, Rafal Jaworowski <raj at semihalf.com> wrote:
>
> On 2009-11-10, at 04:12, David Gibson wrote:
>> Under the new scheme, the "soc" node is really a historical misnomer -
>> it represents just the things within the IMMR, not everything on the
>> SoC.  A number of chips also have the localbus controller as a
>> separate node, likewise within the SoC but not within the IMMR, so not
>> a child of the soc node.
>
> Hm, how do we know whether something belongs under the IMMR/CCSR node or not
> (even though it physically sits there :-)?
>
> Is the 'soc' node going to be named something less confusing then?
>
>> Note also that 4xx chips, unlike the Freescale ones do have the PCI
>> host bridge under the plb node (which represents the main bus on the
>> SoC).
>
> Yea, I noticed, which made me even more confused, so thanks again for
> clarifications.

The whole point of the IMMR node is to group things that are
relocatable together.  It was chosen as a matter of convenience, but
it would be absolutely valid to eliminate the IMMR node entirely just
make all the internal devices peers of the root node.  Except for a
few bugs that would probably be exposed, the current kernel would
parse that device tree just fine.

So, while the expressed ideal is to describe the exact bus topology,
the reality is that there are many reasons why the .dts hierarchy will
not match the physical hierarchy exactly (ie. omitting nodes for
transparent bridges which software has no control over, or adding
nodes to group logically related devices together, or as with
Freescale PCI moving the nodes out entirely because adding all the PCI
ranges to the IMMR node seems 'wrong').  However, it still works
because there are well established conventions, and device drivers
generally stick to the published device binding without making
assumptions about the node layout.  As long as common code parses
'reg' and 'ranges' correctly, then the whole system works.

g.

-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.