PCI bus node location

[Scott Wood]

Rafal Jaworowski wrote:
> On 2009-11-11, at 01:05, David Gibson wrote:
>> Well, yes.  And worse, it means there's two places that need to be
>> adjusted rather than one, if the the IMMR is relocated (which it can
>> be).  But it's a trade-off of this versus the inconvenience of dealing
>> with separate "control" and "bridge" nodes for the PCI and following
>> phandles between them.
> 
> Would the technique with additional control node and a phandle 
> complicate bindings handling much? The clear benefit is the ability to 
> truly reflect hierarchy of devices available within IMMR/CCSR block.

It's not very complicated at all, just a few extra lines of code to follow the 
link.  I had initially done pq2 PCI that way, but it was NACKed because it was 
different:

http://lists.ozlabs.org/pipermail/linuxppc-dev/2007-August/041671.html

>> I don't really understand the question.  As Grant has said the
>> "correct" approach is to have one node representing the control
>> registers - located under the IMMR ("soc") node - and another
>> representing the PCI host bridge itself (which would be in its present
>> location).  There would need to be phandles linking the two.  It
>> doesn't really need any extension to the device tree semantics itself
>> - just a more complex binding for this device.
> 
> Maybe I misunderstood Grant, my impression was that there was possible 
> some 'fixing' of ranges properties (which would be alternative to the 
> control node approach).

But that would introduce even more dual maintenance.

-Scott